Examples Of Sdram Controller Initialization Program - Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual

Examples of SDRAM Controller Initialization Program

The following shows examples of the initialization program for using SDRAM.
Example of initialization routine for 2M words
INIT_SDRAM_16MB:
;;;----------------------- SDRAM access configuration -----------------------------------
;;;*****************************************************************
;;;***************** C33 macro setting part ************************
;;;*****************************************************************
;;; set CEFUNC to use #CE13/14 (upper area)
xld.w %r0,0x48131
bset [%r0],0x1
;;; set area 6,13,14 to internal access
xld.w %r0,0x48132
xld.w %r1,0x2200
ld.h [%r0], %r1
;;; area 6 -> output disable 0.5, wait 2
xld.w %r0,0x4812A
xld.w %r1,0x0237
ld.h [%r0],%r1
;;; available #WAIT
xld.w %r0,0x04812E
bset [%r0],0x0
;;; area 13,14 -> 16bit device, output disable 2.5, wait 0
xld.w %r0,0x048122
xld.w %r1,0x30
ld.h [%r0],%r1
;;;*****************************************************************
;;;************** SDRAM Controller REG setting part ****************
;;;*****************************************************************
;;;-------------------------------------------------
;;;area13 0x2000000 - 0x2FFFFFF(16MB)
;;;area14 0x3000000 - 0x3FFFFFF(16MB)
;;;-------------------------------------------------
;///////////////////////////////////////////
;;; SDRAM area configuration register
xld.w %r0,0x39FFC0
xld.w %r1,0x88
ld.b [%r0],%r1
;///////////////////////////////////////////
;;; SDRAM control register
;;; xld.w %r0,0x39FFC1
;;; xld.w %r1,0xff
;;; ld.b %r0],%r1
;///////////////////////////////////////////
;;; SDRAM address configuration register
xld.w %r0,0x39FFC2
xld.w %r1,0x26
ld.b [%r0],%r1
;///////////////////////////////////////////
;;; SDRAM mode set-up register
xld.w %r0,0x39FFC3
xld.w %r1,0x40
ld.b [%r0],%r1
;///////////////////////////////////////////
;;; SDRAM timing set-up register 1
xld.w %r0,0x39FFC4
xld.w %r1,0x4A
ld.b [%r0],%r1
;///////////////////////////////////////////
;;; SDRAM timing set-up register 2
xld.w %r0,0x39FFC5
xld.w %r1,0x48
ld.b [%r0],%r1
;///////////////////////////////////////////
;;; SDRAM auto refresh count low-order
;;; xld.w %r0,0x39FFC6
;;; xld.w %r1,0xff
;;; ld.b [%r0],%r1
;///////////////////////////////////////////
S1C33L03 FUNCTION PART
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
16 bits 4 banks (16MB) of SDRAM
;
; set area13 to SDRAM area, #SDCE0(#CE13) available
; (16MB area available)
;
; SDRAM self-refresh -> disable, initial sequence ->PRE REF MRS
; Little endian
;
; col 512 / row 4K / bank 4 -> 128Mb[16MB] available
;
;
; 2 CAS Latency ,burst length = 1
;
;
; Tras=2,Trp=1,Trc=2
;
;
; Trcd=1,Trsc=2,Trrd=1
;
register
;
;
;
EPSON
... 1 (See "SDRAM Controller Configuration".)
... 2, 5, B-1
... 3
... 4
... B-2, B-3, B-4
... (note 1)
... (note 2)
... Recommended setting to operate with
25 MHz clock in x1 speed mode
A-1
B-VI
SDRAM
B-VI-2-33