Table of Contents
Advertisement
VNDPF: Vertical non-display status (D7) / Vertical non-display period register (0x39FFEA)
Indicates whether the LCD panel is in a vertical non-display period.
Read "1": Vertical non-display period
Read "0": Vertical display period
Write: Invalid
VNDPF is set to "1" during a vertical non-display period, and set to "0" during a vertical display period. To count
the number of frames in LCD power control, for example, read this bit and count the number of times it is set to
"1". On other occasions, such as when images must be switched without causing the screen to flicker, it is possible
to switch within a vertical non-display period by reading this bit.
At initial reset, VNDPF is set to "0" (vertical display period).
MODRATE[5:0]: MOD rate (D[5:0]) / MOD rate register (0x39FFEB)
Sets the cycle time at which to switch the MOD signal. When this register is 0x0, the MOD signal switches at the
cycle time of the FPFRAME signal. If another period is desired, set the FPLINE pulse-count value.
At initial reset, MODRATE is set to "0x0" (FPFRAME period).
S1ADDR[16:0]: Screen 1 start address register (D0/0x39FFF0, 0x39FFED, 0x39FFEC)
Sets the screen 1 start address. Referencing the beginning of the display memory as address 0x0, write a halfword
address in 16-bit units in normal (landscape) mode, or a byte address in portrait mode. S1ADDR16 (D0/0x39FFF0)
is provided for use in portrait mode. It is unused in normal (landscape) mode, so fix it to "0".
At initial reset, S1ADDR is set to "0x0" (beginning of the display memory).
S1VSIZE[9:0]: Screen 1 vertical size register (D[1:0]/0x39FFF3, 0x39FFF2)
Sets the vertical size of screen 1 in lines. If any number of lines less than the LCD panel's vertical resolution
(LDVSIZE[9:0]) is set in this register, the LCD panel is divided into an upper half from line 1 to line (S1VSIZE -
1) as screen 1, and a lower half from that line down as screen 2. When the screen is not to be divided, set any value
equal to or greater than LDVSIZE in this register, so that only screen 1 will be displayed.
At initial reset, S1VSIZE is set to "0x0".
S2ADDR[15:0]: Screen 2 start address register (0x39FFEF, 0x39FFEE)
Sets the screen 2 start address. Referencing the beginning of the display memory as address 0x0, write a halfword
address in 16-bit units. This register is unused for portrait mode, as split-screen display is not supported in that
mode.
At initial reset, S2ADDR is set to "0x0" (beginning of the display memory).
MADOFS[7:0]: Memory address offset (D[7:0]) / Memory address offset register (0x39FFF1)
Sets an address offset in halfword units to configure a virtual screen in normal (landscape) mode. The offset set
here is added to the address of the last piece of pixel data on each display line, in order to determine the address at
which the next display line starts. The image area is extended in the horizontal direction by a distance equal to this
offset, so that the display area can be panned or scrolled by setting the start-address register as necessary. For
details, refer to "Virtual Screen and View Port".
This register is unused in portrait mode.
At initial reset, MADOFS is set to "0x0" (no virtual screen area).
FIFOEO[3:0]: FIFO empty offset (D[6:3]) / FIFO control register (0x39FFF4)
The LCD controller retrieves data from the display memory into its 16 16-bit FIFO by means of a DMA transfer.
If the amount of data in this FIFO decreases to (0xf - FIFOEO) words or less, the LCD controller sends a DMA
request to the CPU requesting that the data be read. Set the value 8 in FIFOEO.
At initial reset, FIFOEO is set to "0x0".
S1C33L03 FUNCTION PART
VII LCD CONTROLLER BLOCK: LCD CONTROLLER
EPSON
A-1
B-VII
LCDC
B-VII-2-37
Advertisement
Table of Contents
