Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 518

VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
Register name Address Bit
SDRAM 039FFC5 D7–6
timing set-up (B)
register 2
D5
D4–3
D2–0
SDRAM 039FFC6 DF–C
auto refresh (HW) DB
count register DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDRAM 039FFC8 D7–4
self refresh (B) D3
count register D2
D1
D0
SDRAM 039FFC9 D7
advanced (B) D6
control D5
register D4–0
SDRAM 039FFCA D7
status register (B) D6
D5–0
Note: Do not access addresses 0x039FFCB to 0x039FFCD, because they are reserved for testing the
SDRAM controller.
B-VI-2-22
Name Function
SDRTRCD1 SDRAM t spec
RCD
SDRTRCD0
SDRTRSC SDRAM t spec
RSC
SDRTRRD1 SDRAM t spec
RRD
SDRTRRD0
– reserved
– reserved
SDRARFC11 SDRAM auto refresh count [11:0]
SDRARFC10
SDRARFC9
SDRARFC8
SDRARFC7
SDRARFC6
SDRARFC5
SDRARFC4
SDRARFC3
SDRARFC2
SDRARFC1
SDRARFC0
– reserved
SDRSRFC3 SDRAM self refresh count [3:0]
SDRSRFC2
SDRSRFC1
SDRSRFC0
– reserved
SDRSZ SDRAM data path bit width
SDRBI SDRAM bank interleaved access
– reserved
SDRMRS SDRAM mode register set flag
SDRSRM SDRAM current refresh mode
– reserved
Setting
SDRTRCD[1:0] Number of clocks
1 1
1 0
0 1
0 0
1 1 clock 0 2 clocks
SDRTRRD[1:0] Number of clocks
1 1
1 0
0 1
0 0
–
–
0 to 4096
–
2 to 15
–
1 8 bits 0 16 bits
1 Interleaved 0 One bank
–
1 Not finished 0 Done
1 Auto refresh 0 Self refresh
–
EPSON
Init. R/W Remarks
0 R/W
3 0
2
1
4
0 R/W
0 R/W
3 0
2
1
4
– – 0 when being read.
– – 0 when being read.
1 R/W
1
1
1
1
1
1
1
1
1
1
1
– – 0 when being read.
1 R/W This register must
1 not be set less than
1 "0x02".
1
– – 0 when being read.
0 R/W
0 R/W
– – 0 when being read.
1 R
1 R
– – 0 when being read.
S1C33L03 FUNCTION PART