Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 621

Register name Address Bit
High-speed 0048250 DF
DMA Ch.3 (HW) DE
transfer DD
counter DC
register DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
High-speed 0048252 DF
DMA Ch.3 (HW) DE
control register
DD–8
Note:
D7
D) Dual address
D6
mode
D5
S) Single
D4
address
D3
mode
D2
D1
D0
High-speed 0048254 DF
DMA Ch.3 (HW) DE
low-order DD
source address DC
set-up register DB
DA
Note:
D9
D) Dual address
D8
mode
D7
S) Single
D6
address
D5
mode
D4
D3
D2
D1
D0
High-speed 0048256 DF
DMA Ch.3 (HW) DE
high-order DD
source address DC
set-up register
Note:
D) Dual address
DB
mode
DA
S) Single
D9
address
D8
mode
D7
D6
D5
D4
D3
D2
D1
D0
S1C33L03 FUNCTION PART
Name Function
TC3_L7 Ch.3 transfer counter[7:0]
TC3_L6 (block transfer mode)
TC3_L5
TC3_L4 Ch.3 transfer counter[15:8]
TC3_L3 (single/successive transfer mode)
TC3_L2
TC3_L1
TC3_L0
BLKLEN37 Ch.3 block length
BLKLEN36 (block transfer mode)
BLKLEN35
BLKLEN34 Ch.3 transfer counter[7:0]
BLKLEN33 (single/successive transfer mode)
BLKLEN32
BLKLEN31
BLKLEN30
DUALM3 Ch.3 address mode selection
D3DIR D) Invalid
S) Ch.3 transfer direction control
– reserved
TC3_H7 Ch.3 transfer counter[15:8]
TC3_H6 (block transfer mode)
TC3_H5
TC3_H4 Ch.3 transfer counter[23:16]
TC3_H3 (single/successive transfer mode)
TC3_H2
TC3_H1
TC3_H0
S3ADRL15 D) Ch.3 source address[15:0]
S3ADRL14 S) Ch.3 memory address[15:0]
S3ADRL13
S3ADRL12
S3ADRL11
S3ADRL10
S3ADRL9
S3ADRL8
S3ADRL7
S3ADRL6
S3ADRL5
S3ADRL4
S3ADRL3
S3ADRL2
S3ADRL1
S3ADRL0
– reserved
DATSIZE3 Ch.3 transfer data size
S3IN1 D) Ch.3 source address control
S3IN0 S) Ch.3 memory address control
S3ADRH11 D) Ch.3 source address[27:16]
S3ADRH10 S) Ch.3 memory address[27:16]
S3ADRH9
S3ADRH8
S3ADRH7
S3ADRH6
S3ADRH5
S3ADRH4
S3ADRH3
S3ADRH2
S3ADRH1
S3ADRH0
EPSON
Setting Init. R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1 Dual addr 0 Single addr 0
– –
1 Memory WR 0 Memory RD 0
– –
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
– –
1 Half word 0 Byte 0
S3IN[1:0] Inc/dec 0
1 1 Inc.(no init) 0
1 0 Inc.(init)
0 1 Dec.(no init)
0 0 Fixed
X
X
X
X
X
X
X
X
X
X
X
X
APPENDIX: I/O MAP
A-1
Remarks
R/W
R/W
R/W
–
R/W
– Undefined in read.
R/W
R/W
–
R/W
R/W
R/W
B-ap
B-APPENDIX-41