Clock Timer; Configuration Of Clock Timer - Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual

III-7 CLOCK TIMER

Configuration of Clock Timer

The clock timer consists of an 8-bit binary counter that is clocked by a 256-Hz signal derived from the low-speed
(OSC1) oscillation clock f
OSC1
seconds, minutes, hours, and day) to be read out in a software. It can also generate an interrupt using a 32-Hz, 8-Hz,
2-Hz, or 1-Hz (1-second) signal or when a one-minute, one-hour, or one-day count is up, in addition to generating
an alarm at a specified time (minute or hour) or day.
The low-speed (OSC1) oscillation circuit and the clock timer can be kept operating even when the CPU and other
internal peripheral circuits are placed in standby mode (HALT or SLEEP).
Normally, this clock timer should be used for a clock and various other clocking functions.
Figure 7.1 shows the structure of the clock timer.
Note: Since the clock timer is driven by a clock originating from the low-speed (OSC1) oscillation circuit,
this timer cannot be used unless the low-speed (OSC1) oscillation circuit (32.768 kHz, Typ.) is
used.
OSC1
f 256 Hz
OSC1
Divider
oscillation
circuit
32.768 kHz
Clock timer Run/Stop
Clock timer reset
Interrupt request
(to interrupt controller)
S1C33L03 FUNCTION PART
, and second, minute, hour, and day counters, allowing all data (128 Hz to 1 Hz,
128 64 32 16 8 4 2
Hz Hz Hz Hz Hz Hz Hz
Interrupt generation
control circuit
Interrupt/alarm
select circuit
Alarm generation
control circuit
Figure 7.1 Structure of Clock Timer
EPSON
III PERIPHERAL BLOCK: CLOCK TIMER
Internal data bus
6-bit 6-bit
1
seconds minutes
Hz
counter counter
Comparator Comparator Comparator
6-bit minute
comparison
data
5-bit 16-bit
hours day
counter counter
5-bit hour 5-bit day
comparison comparison
data data
B-III-7-1
A-1
B-III
CTM