Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 401

Conditions for port input-interrupt generation
Each port input interrupt can be generated by the edge or level of the input signal. The SEPTx bit of the
edge/level select register (0x402C9) is used for this selection. When SEPTx is set to "1", the FPTx interrupt
will be generated at the signal edge. When SEPTx is set to "0", the FPTx interrupt will be generated by the
input signal level.
Furthermore, the signal polarity can be selected using the SPPTx bit of the input porarity select register
(0x402C8).
With these registers, the port input interrupt condition is decided as shown in Table 9.6.
When the input signal goes to the selected status, the interrupt factor flag FP is set to "1" and, if other
interrupt conditions set by the interrupt controller are met, an interrupt is generated.
S1C33L03 FUNCTION PART
Table 9.6 Port Input Interrupt Condition
SEPTx SPPTx
1 1
1 0
0 1
0 0
EPSON
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
FPTx interrupt condition
Rising edge
Falling edge
High level
Low level
A-1
B-III
I/O
B-III-9-13