Table of Contents
Advertisement
II-7 DBG (Debug Unit)
Debug Circuit
The C33 Core Block has a built-in debug circuit.
This functional block is provided to simply realize an advanced software development environment.
Note: The debug circuit does not work during normal operation. To construct a software development
environment using the debug circuit, the S5U1C33000H (In-Circuit Debugger for S1C33 Family) is
separately required.
I/O Pins of Debug Circuit
Six pins used to exclusively connect the S5U1C33000H (In-Circuit Debugger for S1C33 Family) are reserved for
the debug circuit. The I/O voltage level of these pins is 3.3 V.
Table 7.1 lists the I/O pins of the debug circuit.
Pin name
DCLK
DST2
DST1
DST0
DPCO
DSIO
The DCLK, DST[2:0] and DPCO outputs are extended functions of the I/O port pins P14, P1[2:0] and P13,
respectively. At initial reset, these pins are set as debug signal outputs.
If the debug circuit is not used, these pins can be used for I/O ports or the redefined peripheral circuits by writing
"0" to CFEX[1:0] (D[1:0]) / Port function extension register (0x402DF). Refer to "I/O Ports (P Ports)" for the pin
functions.
Note: When these pins are set as debug signal outputs, only the S5U1C33000H (In-Circuit Debugger for
S1C33 Family) can be connected to these pins. Leave these pins open if the S5U1C33000H is not
connected. For connecting the S5U1C33000H, refer to the "S5U1C33000H Manual (S1C33
Family In-Circuit Debugger)".
Furthermore, the pin status is fixed as shown in the above table after a user reset.
S1C33L03 FUNCTION PART
Table 7.1 I/O Pins of Debug Circuit
I/O
Pull-up
Initial status
O
–
1
O
–
0
O
–
1
O
–
1
O
–
1
I/O With pull-up
1 (Input)
EPSON
II CORE BLOCK: DBG (Debug Unit)
Voltage level
Function
3.3 V
Clock output for debugging
3.3 V
Status output 2 for debugging
3.3 V
Status output 1 for debugging
3.3 V
Status output 0 for debugging
3.3 V
PC output for debugging
3.3 V
Serial I/O for debugging
A-1
B-II
DBG
B-II-7-1
Advertisement
Table of Contents
