Bus Clock - Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual

Bus Clock

The bus clock is generated by the BCU using the CPU system clock output from the clock generator.
Figure 4.17 shows the clock system.
High-speed (OSC3)
OSC3_CLK
oscillation circuit
PLL_CLK
PLL
Low-speed (OSC1)
oscillation circuit
PLL_CLK and CPU_CLK
BCU_CLK
BCU_CLK (#X2SPD = "1", x1 speed mode)
BCU_CLK (#X2SPD = "0", x2 speed mode)
SD_CLK (When #X2SPD = "1")
SD_CLK (When #X2SPD = "0")
S1C33L03 FUNCTION PART
PLLS[1:0] pins
CLKDT[1:0] CLKCHG
1/1–1/8 CPU_CLK
A
OSC3_CLK (PLL: off)
PLL_CLK (PLL: x2 mode)
PLL_CLK (PLL: x4 mode)
A
CPU_CLK (CLKDT = 1/1)
CPU_CLK (CLKDT = 1/2)
CPU_CLK (CLKDT = 1/4)
CPU_CLK (CLKDT = 1/8)
CPU_CLK
1
1
#SDCEx
CPU_CLK
BCU_CLK
SD_CLK (SDRCLK = "1")
SD_CLK (SDRCLK = "0")
SDCKE
#SDCEx
CPU_CLK
BCU_CLK
SD_CLK (SDRCLK = "1")
SD_CLK (SDRCLK = "0")
SDCKE
Figure 4.17 Clock System
II CORE BLOCK: BCU (Bus Control Unit)
#X2SPD pin
CLG
BCU
BCU_CLK
1/1 or 1/2
CPU_CLK
OSC3_CLK
PLL_CLK
SDRAMC
1/1 or 1/2
Refresh
counter
(when the CPU system clock source is OSC3)
1 2 1 2
1 2
3
3
1 Access to the internal RAM
2 Access to the external memory (other than SDRAM)
3 Access to the SDRAM
EPSON
To CPU
Bus clock
BCLKSEL[1:0]
SDRENA
BCLK pin
SD_CLK
1 2
Self refresh
2 1
Self refresh
2 1
B-II-4-17
A-1
B-II
BCU