Sdram Setting Conditions - Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual

VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
B. When using areas 13/14 (CEFUNC = "01")
B-1. A14IO (DD)/Access control register (0x48132) = "1"
This sets areas 13/14 for internal access.
B-2. A14WT[2:0] (D[2:0])/Areas 14–13 set-up register (0x48122) = "000"
This sets areas 13/14 for no-wait access.
B-3. A14SZ (D6)/Areas 14–13 set-up register (0x48122) = SDRSZ (D6)/SDRAM advanced control register
(0x39FFC9)
Use these registers to ensure that the device size of areas 13/14 and that of the SDRAM controller are the
same, and are matched to the SDRAM data width. Both bits select 16 bits when "0" or 8 bits when "1".
B-4. A14DF[1:0] (D[5:4])/Areas 14–13 set-up register (0x48122)
If the system has an external memory device other than an SDRAM connected to it and accesses that memory
device and SDRAM in succession, set the output disable delay time of areas 13/14 to 2.5 cycles (A14DF[1:0]
= "10").
When only the SDRAM is read and no other external device is accessed, set the output disable delay time of
areas 13/14 to 0.5 cycles (A14DF[1:0] = "00") in order to reduce the SDRAM access time.
This completes the BCU settings necessary to access the SDRAM.
Make sure the BCU parameters other than those discussed above are set appropriately for the system.

SDRAM Setting Conditions

The SDRAM interface allows the following conditions to be selected. Although SDRAM can be used in areas 7
and 8 or areas 13 and 14, these conditions are applied to all four areas and cannot be set individually for each area.
Parameter
Area 7/13 configuration SDRAM or Another
Area 8/14 configuration SDRAM or Another
#CE7/13 pin configuration #SDCE0 or #CE7/13
#CE8/14 pin configuration #SDCE1 or #CE8/14
Page size 256, 512 or 1K
Row addressing range 2K, 4K or 8K
Number of banks 4 or 2
Initial command sequence 1. Precharge
2. Refresh
3. Mode register
or
1. Precharge
2. Mode register
3. Refresh
Burst length 1, 2, 4 or 8
CAS latency 2
t 1 to 8 clocks
RAS
t 1 to 4 clocks
RP
t 1 to 8 clocks
RC
t 1 to 4 clocks
RCD
t 1 or 2 clocks
RSC
t 1 to 4 clocks
RRD
Always set CAS latency to 2.
B-VI-2-6
Table 2.4 SDRAM Interface Parameters
Selectable condition Initial setting
Another device
Another device
#CE7/13
#CE8/14
256
2K
2
1. Precharge
2. Refresh
3. Mode register
8
– *
8 clocks
4 clocks
8 clocks
4 clocks
2 clocks
4 clocks
SDRAR0(D7)/SDRAM area configuration register(0x39FFC0)
SDRAR1(D6)/SDRAM area configuration register(0x39FFC0)
SDRPC0(D3)/SDRAM area configuration register(0x39FFC0)
SDRPC1(D2)/SDRAM area configuration register(0x39FFC0)
SDRCA[1:0](D[6:5])
/SDRAM address configuration register(0x39FFC2)
SDRRA[1:0](D[3:2])
/SDRAM address configuration register(0x39FFC2)
SDRBA(D1)
/SDRAM address configuration register(0x39FFC2)
SDRIS(D4)/SDRAM control register(0x39FFC1)
SDRBL[1:0](D[3:2])/SDRAM mode set-up register(0x39FFC3)
SDRCL[1:0](D[6:5])/SDRAM mode set-up register(0x39FFC3)
SDRTRAS[2:0](D[7:5])/SDRAM timing set-up register 1
(0x39FFC4)
SDRTRP[1:0](D[4:3])/SDRAM timing set-up register 1
(0x39FFC4)
SDRTRC[2:0](D[2:0])/SDRAM timing set-up register 1
(0x39FFC4)
SDRTRCD[1:0](D[7:6])/SDRAM timing set-up register 2
(0x39FFC5)
SDRTRSC(D5)/SDRAM timing set-up register 2 (0x39FFC5)
SDRTRRD[1:0](D[4:3])/SDRAM timing set-up register 2
(0x39FFC5)
EPSON
Control bits
S1C33L03 FUNCTION PART