Introduction - Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual

II-1 INTRODUCTION
The core block consists of a functional block C33_CORE including CPU, BCU (Bus Control Unit), ITC
(Interrupt Controller), CLG (Clock Generator) and DBG (Debug Unit), an I/O pad block for external interface, and
an SBUS (Internal Silicon Integration Bus) for interfacing with on-chip Peripheral Macro Cells.
C33 Internal Memory Block
Internal RAM
(Area 0)
Internal ROM
(Area 10)
Note: Internal ROM is not provided in the S1C33L03.
S1C33L03 FUNCTION PART
C33 DMA Block C33 SDRAM Controller Block
C33_DMA
(IDMA, HSDMA) (SDRAM interface)
C33_CORE
(CPU, BCU, ITC, CLG, DBG)
C33_SBUS
C33_ADC
(A/D converter)
C33 Analog Block
Figure 1.1 Core Block
EPSON
II CORE BLOCK: INTRODUCTION
C33 LCD Controller Block
C33_SDRAMC
(LCD panel interface)
C33_PERI
(Prescaler, 8-bit timer, 16-bit timer,
Clock timer, Serial interface, Ports)
C33 Peripheral Block
C33_LCDC
Pads
Pads
C33 Core Block
Pads
B-II-1-1
A-1
B-II
Intro