Table of Contents
Advertisement
Pin name
Pin No.
I/O
FPDAT[7:4]
13–16
O
FPDAT[3:0]
17–20
O
GPO[6:3]
FPFRAME
23
O
FPLINE
24
O
FPSHIFT
25
O
DRDY(MOD)
22
O
(FPSHIFT2)
LCDPWR
26
O
Pin name
Pin No.
I/O
OSC1
68
OSC2
67
O
OSC3
129
OSC4
128
O
PLLS[1:0]
112,113
PLLC
115
–
Pin name
Pin No.
I/O
ICEMD
125
DSIO
117
I/O
#X2SPD
140
#NMI
130
#RESET
69
Note: "#" in the pin names indicates that the signal is low active.
S1C33L03 FUNCTION PART
Table 3.4 List of Pins for LCD Controller
Pull-up
–
4 high-order bits of data bus for 8-bit LCD panels
Data bus for 4-bit LCD panels
–
FPDAT[3:0]: 4 low-order bits of data bus for 8-bit LCD panels
GPO[6:3]:
General-purpose outputs when a 4-bit LCD panel is used
–
Frame pulse output
–
Line pulse output
–
Shift clock output
–
MOD:
LCD backplane bias (for panels other than 8-bit color panel format 1)
FPSHIFT2:
Second shift clock (for 8-bit color panel format 1)
–
LCD power control output (active high)
Table 3.5 List of Pins for Clock Generator
Pull-up
I
–
Low-speed (OSC1) oscillation input (32 kHz crystal oscillator or external clock input)
–
Low-speed (OSC1) oscillation output
I
–
High-speed (OSC3) oscillation input (crystal/ceramic oscillator or external clock input)
–
High-speed (OSC3) oscillation output
I
–
PLL set-up pins
PLLS1
PLLS0
1
0
0
–
Capacitor connecting pin for PLL
Table 3.6 List of Other Pins
Pull-up
/down
I
Pull-
High-impedance control input pin
down
When this pin is set to High, all the output pins go into high-impedance state. This makes
it possible to disable the S1C33 chip on the board.
Pull-up Serial I/O pin for debugging
This pin is used to communicate with the debugging tool S5U1C33000H.
I
–
Clock doubling mode set-up pin
1: CPU clock = bus clock
I
Pull-up NMI request input pin
I
Pull-up Initial reset input pin
EPSON
Function
Function
fin (f
)
OSC3
1
10–25MHz
1
10–12.5MHz
0
PLL is not used
Function
1, 0: CPU clock = bus clock
I OUTLINE: LIST OF PINS
fout (f
)
PSCIN
20–50MHz
40–50MHz
L
2
A-1
B-I
Pin
B-I-3-7
Advertisement
Table of Contents
