I/O Memory Of Sdram Interface - Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual

I/O Memory of SDRAM Interface

Table 2.12 shows the control bits of the SDRAM interface. These registers are mapped into area 6 (0x39FFC0 to
0x39FFCA).
Register name Address Bit
SDRAM area 039FFC0 D7
configuration (B) D6
register D5–4
D3
D2
D1–0
SDRAM 039FFC1 D7
control register (B) D6
D5
D4
D3
D2–0
SDRAM 039FFC2 D7
address (B) D6–5
configuration
register
D4
D3–2
D1
D0
SDRAM 039FFC3 D7
mode set-up (B) D6–5
register
D4
D3–2
D1–0
SDRAM 039FFC4 D7–5
timing set-up (B)
register 1
D4–3
D2–0
S1C33L03 FUNCTION PART
Table 2.12 Control Bits of SDRAM Interface
Name Function
SDRAR0 Area 7/13 configuration
SDRAR1 Area 8/14 configuration
– reserved
SDRPC0 #CE7/13 pin configuration
SDRPC1 #CE8/14 pin configuration
– reserved
SDRENA Enable SDRAM signals
SDRINI Start SDRAM power up
SDRSRF Enable SDRAM self-refresh
SDRIS Initial command sequence
SDRCLK Keep SDCLK during self-refresh
– reserved
– reserved
SDRCA1 SDRAM page size
SDRCA0 (column range)
– reserved
SDRRA1 SDRAM row addressing range
SDRRA0
SDRBA Number of SDRAM banks
– reserved
– reserved
SDRCL1 SDRAM CAS latency
SDRCL0
– reserved
SDRBL1 SDRAM burst length
SDRBL0
– reserved
SDRTRAS2 SDRAM t spec
RAS
SDRTRAS1
SDRTRAS0
SDRTRP1 SDRAM t spec
RP
SDRTRP0
SDRTRC2 SDRAM t spec
RC
SDRTRC1
SDRTRC0
EPSON
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
Setting
1 SDRAM 0 Not SDRAM
1 SDRAM 0 Not SDRAM
–
1 #SDCE0 0 #CE7/13
1 #SDCE1 0 #CE8/14
–
1 Enabled 0 Disabled
1 Start 0 –
1 Enabled 0 Disabled
1 1 precharge 0 1 precharge
2 set reg. 2 refresh
3 refresh 3 set reg.
1 Kept 0 Stopped
–
–
SDRCA[1:0] Page size
1 1 reserved
1 0 1K (SDA[9:0])
0 1 512 (SDA[8:0])
0 0 256 (SDA[7:0])
–
SDRRA[1:0] Addressing range
1 1 reserved
1 0 8K (SDA[12:0])
0 1 4K (SDA[11:0])
0 0 2K (SDA[10:0])
1 4 banks 0 2 banks
–
–
SDRCL[1:0] CAS latency
1 0 2 CAS latency
–
SDRBL[1:0] Burst length
1 1 8
1 0 4
0 1 2
0 0 1
–
SDRTRAS[2:0] Number of clocks
1 1 1 7
1 1 0 6
1 0 1 5
1 0 0 4
0 1 1 3
0 1 0 2
0 0 1 1
0 0 0 8
SDRTRP[1:0] Number of clocks
1 1 3
1 0 2
0 1 1
0 0 4
SDRTRC[2:0] Number of clocks
1 1 1 7
1 1 0 6
1 0 1 5
1 0 0 4
0 1 1 3
0 1 0 2
0 0 1 1
0 0 0 8
Init. R/W Remarks
0 R/W
0 R/W
– – 0 when being read.
0 R/W
0 R/W
– – 0 when being read.
0 R/W
0 R/W 0 when being read.
0 R/W
0 R/W
1 R/W
– – 0 when being read.
– – 0 when being read.
0 R/W
0
– – 0 when being read.
0 R/W
0
0 R/W
– – 0 when being read.
– – 0 when being read.
1 R/W
1
– – 0 when being read.
1 R/W
1
– – 0 when being read.
0 R/W
0
0
0 R/W
0
0 R/W
0
0
B-VI-2-21
A-1
B-VI
SDRAM