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II-5 ITC (Interrupt Controller)
The C33 Core Block contains an interrupt controller, making it possible to control all interrupts generated by
the internal peripheral circuits. This section explains the functions of this interrupt controller centering around the
method for controlling maskable interrupts. For details about the various factors and conditions under which
interrupts are generated, refer to the description of each peripheral circuit in this manual.
Outline of Interrupt Functions
Maskable Interrupts
The ITC can handle 39 kinds of maskable interrupts as shown in the table below.
HEX
Vector number
No.
No.
(Hex address)
1
10 16(Base+40)
Port input interrupt 0
2
11 17(Base+44)
Port input interrupt 1
3
12 18(Base+48)
Port input interrupt 2
4
13 19(Base+4C)
Port input interrupt 3
5
14 20(Base+50)
Key input interrupt 0
6
15 21(Base+54)
Key input interrupt 1
7
16 22(Base+58)
High-speed DMA Ch.0
8
17 23(Base+5C)
High-speed DMA Ch.1
9
18 24(Base+60)
High-speed DMA Ch.2
10
19 25(Base+64)
High-speed DMA Ch.3
11
1A 26(Base+68)
IDMA
–
27–29
reserved
12
1E 30(Base+78)
16-bit programmable timer 0
13
1F 31(Base+7C)
–
32–33
reserved
14
22 34(Base+88)
16-bit programmable timer 1
15
23 35(Base+8C)
–
36–37
reserved
16
26 38(Base+98)
16-bit programmable timer 2
17
27 39(Base+9C)
–
40–41
reserved
18
2A 42(Base+A8)
16-bit programmable timer 3
19
2B 43(Base+AC)
–
44–45
reserved
20
2E 46(Base+B8)
16-bit programmable timer 4
21
2F 47(Base+BC)
–
48–49
reserved
22
32 50(Base+C8)
16-bit programmable timer 5
23
33 51(Base+CC)
24
34 52(Base+D0)
8-bit programmable timer
25
35 53(Base+D4)
26
36 54(Base+D8)
27
37 55(Base+DC)
28
38 56(Base+E0)
Serial interface Ch.0
29
39 57(Base+E4)
30
3A 58(Base+E8)
–
59
reserved
31
3C 60(Base+F0)
Serial interface Ch.1
32
3D 61(Base+F4)
33
3E 62(Base+F8)
–
63
reserved
34
40 64(Base+100) A/D converter
35
41 65(Base+104) Clock timer
–
66–67
reserved
36
44 68(Base+110) Port input interrupt 4
37
45 69(Base+114) Port input interrupt 5
38
46 70(Base+118) Port input interrupt 6
39
47 71(Base+11C) Port input interrupt 7
S1C33L03 FUNCTION PART
Table 5.1 List of Maskable Interrupts
Interrupt system
(Peripheral circuit)
Edge (rising or falling) or level (High or Low)
Edge (rising or falling) or level (High or Low)
Edge (rising or falling) or level (High or Low)
Edge (rising or falling) or level (High or Low)
Rising or falling edge
Rising or falling edge
High-speed DMA Ch.0, end of transfer
High-speed DMA Ch.1, end of transfer
High-speed DMA Ch.2, end of transfer
High-speed DMA Ch.3, end of transfer
Intelligent DMA, end of transfer
–
Timer 0 comparison B
Timer 0 comparison A
–
Timer 1 comparison B
Timer 1 comparison A
–
Timer 2 comparison B
Timer 2 comparison A
–
Timer 3 comparison B
Timer 3 comparison A
–
Timer 4 comparison B
Timer 4 comparison A
–
Timer 5 comparison B
Timer 5 comparison A
Timer 0 underflow
Timer 1 underflow
Timer 2 underflow
Timer 3 underflow
Receive error
Receive buffer full
Transmit buffer empty
–
Receive error
Receive buffer full
Transmit buffer empty
–
A/D converter, end of conversion
Falling edge of 32 Hz, 8 Hz, 2 Hz or 1 Hz signal
1-minuet, 1-hour or specified time count up
–
Edge (rising or falling) or level (High or Low)
Edge (rising or falling) or level (High or Low)
Edge (rising or falling) or level (High or Low)
Edge (rising or falling) or level (High or Low)
EPSON
II CORE BLOCK: ITC (Interrupt Controller)
Interrupt factor
A-1
IDMA
Priority
Ch.
1
High
2
3
4
–
B-II
–
5
6
–
–
–
–
7
ITC
8
–
9
10
–
11
12
–
13
14
–
15
16
–
17
18
19
20
21
22
–
23
24
–
–
25
26
–
27
–
–
28
29
30
31
Low
B-II-5-1
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