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V DMA BLOCK: HSDMA (High-Speed DMA)
Register name
Address
Bit
High-speed
0040298
D7
DMA Ch.0/1
(B)
D6
trigger set-up
D5
register
D4
D3
D2
D1
D0
High-speed
0040299
D7
DMA Ch.2/3
(B)
D6
trigger set-up
D5
register
D4
D3
D2
D1
D0
High-speed
004029A
D7–4
DMA software
(B)
D3
trigger register
D2
D1
D0
K5 function
00402C0
D7–5
select register
(B)
D4
D3
D2
D1
D0
B-V-2-18
Name
Function
HSD1S3
High-speed DMA Ch.1
HSD1S2
trigger set-up
HSD1S1
HSD1S0
HSD0S3
High-speed DMA Ch.0
HSD0S2
trigger set-up
HSD0S1
HSD0S0
HSD3S3
High-speed DMA Ch.3
HSD3S2
trigger set-up
HSD3S1
HSD3S0
HSD2S3
High-speed DMA Ch.2
HSD2S2
trigger set-up
HSD2S1
HSD2S0
–
reserved
HST3
HSDMA Ch.3 software trigger
HST2
HSDMA Ch.2 software trigger
HST1
HSDMA Ch.1 software trigger
HST0
HSDMA Ch.0 software trigger
–
reserved
CFK54
K54 function selection
CFK53
K53 function selection
CFK52
K52 function selection
CFK51
K51 function selection
CFK50
K50 function selection
Setting
0
Software trigger
1
K51 input (falling edge)
2
K51 input (rising edge)
3
Port 1 input
4
Port 5 input
5
8-bit timer Ch.1 underflow
6
16-bit timer Ch.1 compare B
7
16-bit timer Ch.1 compare A
8
16-bit timer Ch.5 compare B
9
16-bit timer Ch.5 compare A
A
SI/F Ch.1 Rx buffer full
B
SI/F Ch.1 Tx buffer empty
C
A/D conversion completion
0
Software trigger
1
K50 input (falling edge)
2
K50 input (rising edge)
3
Port 0 input
4
Port 4 input
5
8-bit timer Ch.0 underflow
6
16-bit timer Ch.0 compare B
7
16-bit timer Ch.0 compare A
8
16-bit timer Ch.4 compare B
9
16-bit timer Ch.4 compare A
A
SI/F Ch.0 Rx buffer full
B
SI/F Ch.0 Tx buffer empty
C
A/D conversion completion
0
Software trigger
1
K54 input (falling edge)
2
K54 input (rising edge)
3
Port 3 input
4
Port 7 input
5
8-bit timer Ch.3 underflow
6
16-bit timer Ch.3 compare B
7
16-bit timer Ch.3 compare A
8
16-bit timer Ch.5 compare B
9
16-bit timer Ch.5 compare A
A
SI/F Ch.1 Rx buffer full
B
SI/F Ch.1 Tx buffer empty
C
A/D conversion completion
0
Software trigger
1
K53 input (falling edge)
2
K53 input (rising edge)
3
Port 2 input
4
Port 6 input
5
8-bit timer Ch.2 underflow
6
16-bit timer Ch.2 compare B
7
16-bit timer Ch.2 compare A
8
16-bit timer Ch.4 compare B
9
16-bit timer Ch.4 compare A
A
SI/F Ch.0 Rx buffer full
B
SI/F Ch.0 Tx buffer empty
C
A/D conversion completion
–
1 Trigger
0 Invalid
–
1 #DMAREQ3 0 K54
1 #DMAREQ2 0 K53
1 #ADTRG
0 K52
1 #DMAREQ1 0 K51
1 #DMAREQ0 0 K50
EPSON
Init. R/W
Remarks
0
R/W
0
0
0
0
R/W
0
0
0
0
R/W
0
0
0
0
R/W
0
0
0
–
–
0 when being read.
0
W
0
W
0
W
0
W
–
–
0 when being read.
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
S1C33L03 FUNCTION PART
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