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A.3 ROM and Burst ROM
Burst ROM and mask ROM interface setup examples
Operating
frequency
Wait cycle
20MHz
25MHz
33MHz
Burst ROM and mask ROM interface timing
Burst ROM and mask ROM interface
Parameter
Access time
#CE output delay time
#OE output delay time
Burst access time
Output disable delay time
ROM: 100ns, CPU: 33MHz, normal read
BCLK
A[23:0]
#CE9, 10
#RD
D[15:0]
ROM: 100ns, CPU: 33MHz, burst read
BCLK
Normal read cycle
A[23:0]
#CE9, 10
#RD
D[15:0]
S1C33L03 PRODUCT PART
APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS
Normal read cycle
Read cycle
2
3
3
4
4
5
Symbol
Min.
t
–
ACC
t
–
CE
t
–
OE
t
–
BAC
t
0
DF
t
ACC
t
CE
t
OE
t
BAC
RD data
EPSON
Burst read cycle
Wait cycle
Read cycle
1
1
2
33MHz
Max.
Cycle
Time
Cycle
100
5
150
100
5
150
50
4.5
135
50
3
90
40
1.5
45
RD data
Burst read cycle
t
BAC
RD data
RD data
Output disable
delay cycle
2
1.5
2
1.5
3
1.5
25MHz
20MHz
Time
Cycle
Time
4
160
3
150
4
160
3
150
3.5
140
2.5
125
2
80
2
100
1.5
60
1.5
75
t
DF
t
BAC
t
DF
RD data
A-121
A-1
A-ap
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