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I-1 INTRODUCTION
The Function Part gives a detailed description of the various function blocks built into the Seiko Epson original
32-bit microcomputer S1C33L03.
The S1C33L03 employs a RISC type CPU, and has a powerful instruction set capable of compilation into compact
code, despite the small CPU core size.
The S1C33L03 has the following features:
• Small CPU core:
• Fast and high performance: DC to 50 MHz operation
• Strong instruction set:
• Execution cycle:
• MAC function:
• Registers:
• Memory space:
• External bus I/F:
• Interrupts:
• Reset, boot:
• Power down mode:
• Others:
• User logic interface:
S1C33L03 FUNCTION PART
25K gates
16-bit fixed length, 105 basic instructions
Major instructions are executed in 1 cycle per instruction
16 bits 16 bits + 64 bits, 2 clock per MAC (25 MOPS in 50 MHz)
32 bits 16 general registers and 32 bits 5 special registers
256M bytes (28 bits) linear space, code-data-IO shared type
15 configurable memory areas
Direct connection to external memory
Reset, NMI, up to 128 external interrupts, 4 software interrupts, 2 exceptions
Cold reset, hot reset
Sleep, Halt
Little endian (partial big endian can be configured)
Harvard architecture (fetch, load/store parallel execution)
Programmable wait state (up to 7 cycles)
#WAIT pin hand shake is possible.
Large memory space for the user logic (up to 16M bytes)
BCU configuration registers allow internal use of the external areas (Areas 4 to 18).
Many interrupt requests from the user logic are acceptable.
EPSON
I OUTLINE: INTRODUCTION
B-I-1-1
A-1
B-I
Intro
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