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II CORE BLOCK: ITC (Interrupt Controller)
Interrupt Priority Register and Interrupt Levels
The interrupt priority register is a 3-bit register provided for each interrupt system. It allows the interrupt levels of a
given interrupt system to be set in the range of 0 to 7. The default priorities shown in Table 5.1 can be modified
according to system requirements by this setting.
The value set in this register is used by the interrupt controller and the CPU as described below.
Roles of the interrupt priority register in the interrupt controller
If two or more interrupt factors that have been enabled by the interrupt enable register occur simultaneously,
the interrupt factor in the interrupt system whose interrupt priority register contains the greatest value is
allowed by the interrupt controller to signal an interrupt request to the CPU.
If an interrupt factor occurs in two or more interrupt systems having the same value, the interrupt priority is
resolved according to the default priorities in Table 5.1. Interrupt factors in the same interrupt system also
have their priorities resolved according to the order in Table 5.1.
Other interrupt factors are kept pending until all interrupts of higher priority are accepted by the CPU.
When outputting an interrupt request signal to the CPU, the interrupt controller outputs the content of the
interrupt priority register to the CPU along with it.
If another interrupt factor of higher priority occurs during outputting an interrupt request signal, the interrupt
controller changes the vector number and interrupt level to those of the new interrupt factor before they are
output to the CPU. The first interrupt request is left pending.
Roles of the interrupt priority register in CPU processing
The CPU compares the content of the interrupt priority register received from the interrupt controller with the
interrupt level that is set in the IL of the PSR to determine whether or not to accept the interrupt request.
IE bit = "1" & IL < interrupt priority register: the interrupt request is accepted
IE bit = "1" & IL interrupt priority register: the interrupt request is rejected
Before interrupts can be controlled by an interrupt level, the interrupt disabling level must be written to the IL.
For example, if the value written to the IL is 3, only the interrupts whose interrupt levels written in the
interrupt priority register are 4 or more will be accepted.
When an interrupt is accepted, the interrupt level that is set in its interrupt priority register is written to the IL.
As a result, the interrupt requests below that interrupt level can no longer be accepted.
If the interrupt priority register for an interrupt is set to "0", the interrupt is disabled. However, invoking
IDMA by means of an interrupt factor works fine.
Notes: • As the S1C33000 Core CPU function, the IL allows interrupt levels to be set in the range of 0 to
15. However, since the interrupt priority register in the C33 Core Block consists of three bits,
interrupt levels in each interrupt system can only be set for up to 8.
• Multiple interrupts can also be handled by rewriting the interrupt level to the IL in the interrupt
processing routine. However, if the interrupt level of the IL is set below the current level and the
IE is set to enable interrupts before resetting the interrupt factor flag after an interrupt has
occurred, the same interrupt may occur again.
B-II-5-8
EPSON
S1C33L03 FUNCTION PART
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