Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 463

Register name Address Bit
High-speed 004824A DF
DMA Ch.2 (HW) DE
high-order
destination
address set-up
register DD
DC
Note:
D) Dual address
mode
S) Single
DB
address
DA
mode
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
High-speed 004824C DF–1
DMA Ch.2 (HW)
enable register D0
High-speed 004824E DF–1
DMA Ch.2 (HW)
trigger flag D0
register
High-speed 0048250 DF
DMA Ch.3 (HW) DE
transfer DD
counter DC
register DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
High-speed 0048252 DF
DMA Ch.3 (HW) DE
control register
DD–8
Note:
D7
D) Dual address
D6
mode
D5
S) Single
D4
address
D3
mode
D2
D1
D0
S1C33L03 FUNCTION PART
Name Function
D2MOD1 Ch.2 transfer mode
D2MOD0
D2IN1 D) Ch.2 destination address
D2IN0 control
S) Invalid
D2ADRH11 D) Ch.2 destination
D2ADRH10 address[27:16]
D2ADRH9 S) Invalid
D2ADRH8
D2ADRH7
D2ADRH6
D2ADRH5
D2ADRH4
D2ADRH3
D2ADRH2
D2ADRH1
D2ADRH0
– reserved
HS2_EN Ch.2 enable
– reserved
HS2_TF Ch.2 trigger flag clear (writing)
Ch.2 trigger flag status (reading)
TC3_L7 Ch.3 transfer counter[7:0]
TC3_L6 (block transfer mode)
TC3_L5
TC3_L4 Ch.3 transfer counter[15:8]
TC3_L3 (single/successive transfer mode)
TC3_L2
TC3_L1
TC3_L0
BLKLEN37 Ch.3 block length
BLKLEN36 (block transfer mode)
BLKLEN35
BLKLEN34 Ch.3 transfer counter[7:0]
BLKLEN33 (single/successive transfer mode)
BLKLEN32
BLKLEN31
BLKLEN30
DUALM3 Ch.3 address mode selection
D3DIR D) Invalid
S) Ch.3 transfer direction control
– reserved
TC3_H7 Ch.3 transfer counter[15:8]
TC3_H6 (block transfer mode)
TC3_H5
TC3_H4 Ch.3 transfer counter[23:16]
TC3_H3 (single/successive transfer mode)
TC3_H2
TC3_H1
TC3_H0
EPSON
V DMA BLOCK: HSDMA (High-Speed DMA)
Setting Init. R/W
D2MOD[1:0] Mode 0
1 1 Invalid 0
1 0 Block
0 1 Successive
0 0 Single
D2IN[1:0] Inc/dec 0
1 1 Inc.(no init) 0
1 0 Inc.(init)
0 1 Dec.(no init)
0 0 Fixed
X
X
X
X
X
X
X
X
X
X
X
X
– –
1 Enable 0 Disable 0
– –
1 Clear 0 No operation 0
1 Set 0 Cleared
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1 Dual addr 0 Single addr 0
– –
1 Memory WR 0 Memory RD 0
– –
X
X
X
X
X
X
X
X
A-1
Remarks
R/W
R/W
R/W
– Undefined in read.
R/W
– Undefined in read.
R/W
R/W
R/W
R/W
–
R/W
– Undefined in read.
R/W
B-V
HSDMA
B-V-2-25