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III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT
SOSC1: Low-speed (OSC1) oscillation control (D0) / Power control register (0x40180)
Turns the low-speed (OSC1) oscillation on or off.
Write "1": OSC1 oscillation turned on
Write "0": OSC1 oscillation turned off
Read: Valid
The oscillation of the low-speed (OSC1) oscillation circuit is stopped by writing "0" to SOSC1, and started again
by writing "1".
Since a duration of maximum three seconds is required for oscillation to stabilize after the oscillation has been
restarted, at least this length of time must pass before the OSC1 clock can be used.
Writing to SOSC1 is allowed only when CLGP[7:0] is set to "0b10010110". Note also that if the CPU is operating
using the OSC1 clock, writing "0" to SOSC1 is ignored and the oscillation is not turned off.
At initial reset, SOSC1 is set to "1" (OSC1 oscillation turned on).
CLKCHG: CPU operating clock switch (D2) / Power control register (0x40180)
Selects the CPU operating clock.
Write "1": OSC3 clock
Write "0": OSC1 clock
Read: Valid
The OSC3 clock is selected as the CPU operating clock by writing "1" to CLKCHG, and OSC1 is selected by
writing "0". The operating clock can be switched over in this way only when both the high-speed (OSC3) and low-
speed (OSC1) oscillation circuits are on. In addition, writing to CLKCHG is effective only when CLGP[7:0] is set
to "0b10010110". Immediately after the oscillation circuit has started oscillating, wait for the oscillation to stabilize
before switching over the CPU operating clock.
At initial reset, CLKCHG is set to "1" (OSC3 clock).
For controlling the high-speed (OSC3) oscillation circuit, refer to "CLG (Clock Generator)" in the Core Block.
HLT2OP: HALT clock option (D3) / Clock option register (0x40190)
Select a HALT condition (basic mode or HALT2 mode).
Write "1": HALT2 mode
Write "0": Basic mode
Read: Valid
When "1" is written to HLT2OP, the CPU will enter HALT2 mode when the HALT instruction is executed. When
"0" is written, the CPU will enter basic mode.
Writing to HLT2OP is allowed only when CLGP[7:0] is set to "0b10010110".
At initial reset, HLT2OP is set to "0" (basic mode).
B-III-6-6
EPSON
S1C33L03 FUNCTION PART
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