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DRAM refresh when bus ownership control is released
In systems where DRAM is connected directly, a refresh request could arise while control of the bus
ownership is released from the CPU. In such a case, take one of the corrective measures described below.
• Monitoring the output signal of the 8-bit programmable timer 0
The underflow signal (DRAM refresh request) of the 8-bit programmable timer 0 can be output from the P10
I/O port pin.
If a refresh request arises while the external bus master is monitoring this output, release #BUSREQ back
high to drop the request for bus ownership control.
Start a DRAM refresh cycle when control of the bus ownership is returned to the CPU.
To direct the P10 pin in order to output the underflow signal of the 8-bit programmable timer 0, write "1" to
CFP10 (D0) / P1 function select register (0x402D4 [Byte]) and IOC10 (D0) / P1 I/O control register
(0x402D6 [Byte]). Also, to output the underflow signal to an external device, write "1" to PTOUT0 (D2) / 8-
bit Timer 0 control register (0x40160 [Byte]). For details about output control, refer to "8-Bit Programmable
Timers".
• Monitoring the #BUSGET signal
The #BUSGET signal can be output from the P31 I/O port pin.
The #BUSGET signal is derived from logical sum of the following signals:
1. DRAM refresh request signal (output from the 8-bit programmable timer 0)
2. Interrupt request signal from the interrupt controller to the CPU
3. Startup request signal from the interrupt controller to the IDMA
If the #BUSGET signal is found to be active when the external bus master is monitoring it, release #BUSREQ
back high to drop the request for bus ownership control.
When using the #BUSGET signal to only monitor a refresh request, set the interrupt controller in such a way
that no interrupt request or IDMA startup request will be generated.
To direct the P31 pin for output of the #BUSGET signal, write "1" to CFEX3 (D3) / Port function extension
register (0x402DF [Byte]).
Power-down Control by External Device
In addition to requesting the releasing of bus ownership control described above, it is possible to place the CPU in
a HALT state by using the #BUSREQ signal. This allows the CPU to be stopped during bus operation by an
external bus master in order to conserve power.
This function is enabled by writing "1" to SEPD (D1) / Bus control register (0x4812E).
If SEPD = "1", the CPU and the BCU stop operating when the #BUSREQ pin is lowered, thus entering a HALT
state. This HALT state is not cleared by an interrupt from the internal peripheral circuits and remains set until the
#BUSREQ pin is released back high. Unlike in the case of ordinary releasing of the bus by #BUSREQ, the address
bus and bus control signals are not placed in high-impedance state.
For a DRAM refresh request that may arise in this HALT state, take one of the corrective measures described
above.
S1C33L03 FUNCTION PART
II CORE BLOCK: BCU (Bus Control Unit)
EPSON
A-1
B-II
BCU
B-II-4-33
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