Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 70

4 PERIPHERAL CIRCUITS
Register name Address Bit
High-speed 0048238 DF
DMA Ch.1 (HW) DE
low-order DD
destination DC
address set-up DB
register DA
D9
Note:
D8
D) Dual address
D7
mode
D6
S) Single
D5
address
D4
mode
D3
D2
D1
D0
High-speed 004823A DF
DMA Ch.1 (HW) DE
high-order
destination
address set-up
register DD
DC
Note:
D) Dual address
mode
S) Single
DB
address
DA
mode
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
High-speed 004823C DF–1
DMA Ch.1 (HW)
enable register D0
High-speed 004823E DF–1
DMA Ch.1 (HW)
trigger flag D0
register
A-54
Name Function
D1ADRL15 D) Ch.1 destination address[15:0]
D1ADRL14 S) Invalid
D1ADRL13
D1ADRL12
D1ADRL11
D1ADRL10
D1ADRL9
D1ADRL8
D1ADRL7
D1ADRL6
D1ADRL5
D1ADRL4
D1ADRL3
D1ADRL2
D1ADRL1
D1ADRL0
D1MOD1 Ch.1 transfer mode
D1MOD0
D1IN1 D) Ch.1 destination address
D1IN0 control
S) Invalid
D1ADRH11 D) Ch.1 destination
D1ADRH10 address[27:16]
D1ADRH9 S) Invalid
D1ADRH8
D1ADRH7
D1ADRH6
D1ADRH5
D1ADRH4
D1ADRH3
D1ADRH2
D1ADRH1
D1ADRH0
– reserved
HS1_EN Ch.1 enable
– reserved
HS1_TF Ch.1 trigger flag clear (writing)
Ch.1 trigger flag status (reading)
Setting
D1MOD[1:0] Mode
1 1 Invalid
1 0 Block
0 1 Successive
0 0 Single
D1IN[1:0] Inc/dec
1 1 Inc.(no init)
1 0 Inc.(init)
0 1 Dec.(no init)
0 0 Fixed
–
1 Enable 0 Disable
–
1 Clear 0 No operation
1 Set 0 Cleared
EPSON
Init. R/W Remarks
X R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0 R/W
0
0 R/W
0
X R/W
X
X
X
X
X
X
X
X
X
X
X
– – Undefined in read.
0 R/W
– – Undefined in read.
0 R/W
S1C33L03 PRODUCT PART