Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 107

EDO DRAM random access cycle (basic cycle)
BCLK
t
AD
A[23:0]
#RAS
#HCAS/
#LCAS
#RD
D[15:0]
#WE
D[15:0]
t
1 is measured with respect to the first signal change (negation) of either the #RD or the #RASx signals.
RDH
EDO DRAM page access cycle
RAS1
BCLK
t
AD
A[23:0]
#RAS
#HCAS/
#LCAS
#RD
D[15:0]
#WE
D[15:0]
t
1 is measured with respect to the first signal change from among the #RD (negation), #RASx (negation)
RDH
and #CAS (fall) signals.
S1C33L03 PRODUCT PART
Data transfer #1
RAS1 CAS1
t
AD
t
RASD1
t
RASW
t
CASD1
t
RDD1
t
RDW2
t
RACE
t
ACCE
t
WRD1
t
WRW2
t
WDD1
Data transfer #1
CAS1
t
AD
t
RASD1
t
RASW
t
CASD1
t
CASW
t
RDD1
t
RDW2
t
CACE
t
RACE
t
ACCE
t
WRD1
t
WRW2
t
WDD1
EPSON
8 ELECTRICAL CHARACTERISTICS
PRE1
(precharge)
t
AD
t
RASD2
t
CASD2
t
CASW
t
RDD3
t
CACE
1
t t
RDS2 RDH
t
WRD3
t
WDD2
Data transfer #2
CAS2 PRE1
(precharge)
t
AD
t
CASD2
t
ACCE
t t t
RDS RDH RDS
t t
WDD2 WDD2
Next data transfer
RAS1' CAS1'
Next data transfer
RAS1'
t
RASD2
t
RDD3
1
t
RDH
t
WRD3
A-91
A-1
A-8