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VII LCD CONTROLLER BLOCK: LCD CONTROLLER
Register name
Address
Bit
LCDC
039FFFD
D7
system control
(B)
D6
register
D5
D4
D3
D2
D1
D0
Note: Addresses 0x39FFFE and 0x39FFFF are assigned for the purpose of inspecting the LCD
controller. Writing data to these addresses may damage the LCD controller and the LCD panel to
which the LCD controller is connected. Therefore, make sure data is never written to that location.
PCODE[5:0]: Product code (D[7:2]) / Revision code register (0x39FFE0)
The LCD controller's product code (0b000010) is written here. These bits are read-only, and writing to them has
no effect.
RCODE[1:0]: Revision code (D[1:0]) / Revision code register (0x39FFE0)
The LCD controller's revision code (0b00) is written here. These bits are read-only, and writing to them has no
effect.
LDCOLOR: Color/monochrome select (D5) / LCDC mode register 0 (0x39FFE1)
Selects the type of connected LCD panel (color or monochrome).
Write "1": Color panel
Write "0": Monochrome panel
Read: Valid
Setting LDCOLOR to "1" selects a color panel drive method, and setting it to "0" selects a monochrome panel
drive method.
At initial reset, LDCOLOR is set to "0" (monochrome panel).
FPSMASK: Mask FPSHIFT signal (D2) / LCDC mode register 0 (0x39FFE1)
Selects the FPSHIFT mask (effective only for color LCD panels).
Write "1": Masked
Write "0": Output
Read: Valid
When FPSMASK is set to "1", the FPSHIFT signal is masked and is not output during the non-display period.
When FPSMASK is set to "0", the FPSHIFT signal is output even during the non-display period. This setting is
effective only for color LCD panels (LDCOLOR = "1"). When a monochrome LCD panel is used, the FPSHIFT
signal is not masked regardless of the setting of this bit.
At initial reset, FPSMASK is set to "0" (output).
LDDW[1:0]: LCD data width/format (D[1:0]) / LCDC mode register 0 (0x39FFE1)
Selects the LCD panel's data width and format. The contents of selection, including that of LDCOLOR, are listed
in Table 2.22.
LDCOLOR
0
1
At initial reset, LDDW is set to "0b00" (4-bit panel).
B-VII-2-34
Name
Function
VRAMAR
VRAM area select
VRAMWT2
VRAM wait control
VRAMWT1
(number of wait cycles for SRAM)
VRAMWT0
EDMAEN
External DMA enable
BREQEN
External bus-request enable
LCDCST
A0/BSL select
LCDCEC
Big/little endian select
Table 2.22 Selection of LCD Panels
LDDW1
LDDW0
0
0
1
1
0
1
0
0
1
1
0
1
Setting
1 Area 8
0 Area 7
0–7
1 Enabled
0 Disabled
1 Enabled
0 Disabled
1 BSL
0 A0
1 Big endian
0 Little endian
LCD panel
Mono Single 4-bit passive LCD
Mono Single 8-bit passive LCD
Reserved
Reserved
Color Single 4-bit passive LCD
Color Single 8-bit passive LCD format 1
Reserved
Color Single 8-bit passive LCD format 2
EPSON
Init. R/W
Remarks
0
R/W
0
R/W
0
0
0
R/W
0
R/W
0
R/W
0
R/W
S1C33L03 FUNCTION PART
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