Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 132

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS
DRAM: 70ns, CPU: 25/20MHz, random read/write cycle
BCLK
A[11:0]
#RAS
#CAS
#RD
D[15:0](RD)
#WE
D[15:0](WR)
DRAM: 70ns, CPU: 25/20MHz, page-mode read/write cycle
BCLK
A[11:0]
#RAS
#CAS
#RD
D[15:0](RD)
#WE
D[15:0](WR)
DRAM: 70ns, CPU: 25/20MHz, CAS-before-RAS refresh cycle
BCLK
#RAS
#CAS
A-116
RAS cycle CAS cycle
1
ROW #1
WR data
RAS cycle CAS cycle
1 2
ROW #1 COL #1
WR data
RPC delay Fixed Refresh RAS pulse width
1 1
t t
RPC CSR
RAS precharge
2 2
COL #1
t
RAS
RD data
CAS cycle
2
COL #2
t
RAS
RD data RD data
WR data
RAS precharge
2
t
RAS
t
CHR
EPSON
ROW #2
RAS precharge
2
2
S1C33L03 PRODUCT PART