Table of Contents
Advertisement
Refresh Mode
The SDRAM controller supports two SDRAM refresh modes: auto refresh and self-refresh.
Auto refresh
The SDRAM controller incorporates a 12-bit auto refresh counter. This counter continues counting on OSC3
clock edges, and when a specified count is reached, commands are sent to the SDRAM that precharges and
auto-refreshes all banks. The counter is reset at that time, and starts counting for the next refresh period. The
counter is also reset by self-refresh.
The auto-refresh period is determined by the OSC3 clock frequency and the count value set in the SDRARFC
[11:0] (D[B:0])/Auto refresh count register (0x39FFC6). For SDRARFC, set the appropriate value meeting
the specifications of your SDRAM. The count value is obtained by the equation below.
RFP
SDRARFC
––––––––
ROWS
RFP:
Maximum refresh period [s]
ROWS: Row address size
f
: OSC3 clock frequency [Hz]
OSC3
BL:
Burst length [word]
CL:
CAS latency [Number of SD_CLK cycles]
t
:
PRECHARGE command period [Number of SD_CLK cycles]
RP
t
:
ACTIVE to READ or WRITE delay time [Number of SD_CLK cycles]
RCD
If RFP = 64 ms, ROWS = 4,096, f
value to set is calculated as follows:
0.064
SDRARFC
––––––––
4,096
Therefore, set any value equal to or less than 286 (0x11E) for SDRARFC.
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]
S1C33L03 FUNCTION PART
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
f
- BL - CL - 2
t
- t
OSC3
RP
= 20 MHz, BL = 8, CL = 3, t
OSC3
20,000,000 - 8 - 3 - 2
4 - 4 - 3 = 286
NOP
PALL NOP
REF
H
L
t
RP
Figure 2.15 Auto Refresh
EPSON
- 3
RCD
= 4, and t
= 4, for example, the
RP
RCD
NOP
REF
NOP
t
RC
A-1
B-VI
SDRAM
B-VI-2-17
Advertisement
Table of Contents
