Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 506

VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
Enabling/disabling bank interleaved access
A bank cannot be accessed at the same time it is being precharged, so another bank may be accessed during
that period, which results in increased access speed. For this purpose, the SDRAM controller supports a
feature known as Bank Interleaved Access.
Specify whether or not to use this feature with the SDRBI (D5)/SDRAM advanced control register
(0x39FFC9).
SDRBI = "1": Bank interleaved access function is used
SDRBI = "0": Bank interleaved access function is not used (one bank only is accessed at a time)
When SDRBI = "0"
BCLK
Command
SDCKE H
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]
Bank 1
Bank 2
When SDRBI = "1"
BCLK
Command
SDCKE H
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]
Bank 1
Bank 2
When SDRBI is set to "0", the SDRAM controller issues the precharge command every time the bank to be
accessed is changed. This reduces current consumption than that of the bank interleaved access, so set SDRBI
to "0" if bank is hardly changed through a series of access.
B-VI-2-10
ACTV READ
BA1 BA1
ROW1
ROW1 COLn
Active Read
ACTV ACTV READ
BA1 BA2 BA1
ROW1 ROW2
ROW1 ROW2 COLn
Active Read
Active
t
CAS latency
RRD
Figure 2.6 Bank Interleaved Access
EPSON
NOP PRE NOP ACTV NOP
BA1 BA2
ROW2
ROW2
D
(n)
Precharge
Active
NOP READ NOP PRE NOP
BA2 BA1
COLm
D D
(n) (m)
Precharge
Read
t
RP
= 2 (Bank 1 cannot be accessed)
(CAS latency = 2, t = 2)
RCD
READ NOP PRE NOP ACTV
BA2 BA2 BA1
ROW3
CONm ROW3
D
(m)
Read Precharge
(CAS latency = 2, t = 2)
RCD
ACTV NOP READ NOP
BA1 BA1
ROW3
ROW3 COLl
D
(l)
S1C33L03 FUNCTION PART