Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 242

II CORE BLOCK: ITC (Interrupt Controller)
Register name Address Bit
Areas 10–9 0048126 DF
set-up register (HW) DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
The following collectively explains the basic functions of each control register/bit. For details about individual
interrupt systems and the contents classified by an interrupt factor, refer to the descriptions of the peripheral
circuits in this manual.
Pxxx2–Pxxx0: Interrupt priority register
Set the priority levels of each interrupt system in the range of 0 to 7.
If this register is set below the IL value of the PSR, no interrupt is generated. The value of this register when
initially reset is indeterminate.
Exxx: Interrupt enable register
Enable or disable interrupt generation to the CPU.
Write "1": Interrupt enabled
Write "0": Interrupt disabled
Read: Valid
Interrupts are enabled when the corresponding bits of this register are set to "1" and are disabled when the bits are
set to "0".
For the interrupt factors used to request IDMA invocation or clear the standby mode, the corresponding interrupt
enable register bit must be set for interrupt enable.
When initially reset, this register is set to "0" (interrupt disabled).
B-II-5-18
Name Function
– reserved
A10IR2 Area 10 internal ROM size
A10IR1 selection
A10IR0
– reserved
A10BW1 Areas 10–9
A10BW0 burst ROM
burst read cycle wait control
A10DRA Area 10 burst ROM selection
A9DRA Area 9 burst ROM selection
A10SZ Areas 10–9 device size selection
A10DF1 Areas 10–9
A10DF0 output disable delay time
– reserved
A10WT2 Areas 10–9 wait control
A10WT1
A10WT0
Setting
–
A10IR[2:0] ROM size
1 1 1 2MB
1 1 0 1MB
1 0 1 512KB
1 0 0 256KB
0 1 1 128KB
0 1 0 64KB
0 0 1 32KB
0 0 0 16KB
–
A10BW[1:0] Wait cycles
1 1
1 0
0 1
0 0
1 Used 0 Not used
1 Used 0 Not used
1 8 bits 0 16 bits
A10DF[1:0] Number of cycles
1 1
1 0
0 1
0 0
–
A10WT[2:0] Wait cycles
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
EPSON
Init. R/W Remarks
– – 0 when being read.
1 R/W
1
1
– – 0 when being read.
0 R/W
3 0
2
1
0
0 R/W
0 R/W
0 R/W
1 R/W
3.5 1
2.5
1.5
0.5
– – 0 when being read.
1 R/W
7 1
6 1
5
4
3
2
1
0
S1C33L03 FUNCTION PART