Table of Contents
Advertisement
8-bit single color panel timing (Format 1)
FPFRAME
FPLINE
FPDAT[7:0]
FPLINE
FPSHIFT
FPSHIFT2
FPDAT7
1-R1
FPDAT6
1-B1
FPDAT5
1-G2
FPDAT4
1-R3
FPDAT3
1-B3
FPDAT2
1-G4
FPDAT1
1-R5
FPDAT0
1-B5
Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640
VDP
= Vertical Display Period
VNDP = Vertical Non-Display Period
HDP
= Horizontal Display Period
HNDP = Horizontal Non-Display Period = (HNDP[4:0] + 4)
S1C33L03 PRODUCT PART
VDP
Line 1
Line 2
Line 3
Line 4
1-G1
1-G6
1-B6
1-B11
1-R12
1-R2
1-R7
1-G7
1-G12
1-B12
1-B2
1-B7
1-R8
1-R13
1-G13
1-G3
1-G8
1-B8
1-B13
1-R14
1-R4
1-R9
1-G9
1-G14
1-B14
1-B4
1-B9
1-R10
1-R15
1-G15
1-G5
1-G10
1-B10
1-B15
1-R16
1-R6
1-R11
1-G11
1-G16
1-B16
480 panel
= LDVSIZE[9:0] + 1 (lines)
= VNDP[5:0] (lines)
= (LDHSIZE[5:0] + 1)
EPSON
8 ELECTRICAL CHARACTERISTICS
Line 479
Line 480
HDP
LDVSIZE[9:0] (0x39FFE5, D[1:0]/0x39FFE6)
VNDP[5:0] (D[5:0]/0x39FFEA)
16 (Ts)
LDHSIZE[5:0] (D[5:0]/0x39FFE4)
8 (Ts)
HNDP[4:0] (D[4:0]/0x39FFE7)
VNDP
Line 1
Line 2
HNDP
1-R636
1-B636
1-G637
1-R638
1-B638
1-G639
1-R640
1-B640
A-103
A-1
A-8
Advertisement
Table of Contents
