Burst Read Cycle - Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual

Burst Read Cycle

Except when the burst length is set to 1 (SDRBL[1:0] "00"), the SDRAM controller always reads data from the
SDRAM in bursts.
Figure 2.11 shows several examples of timing charts when reading out 4-word data from the same row address in
varying burst lengths.
Example of parameter settings: CAS latency = 2, t
(1) Burst length = 8
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]
(2) Burst length = 4
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]
(3) Burst length = 2
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]
S1C33L03 FUNCTION PART
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
= 2 cycles, t
RCD
NOP PRE NOP ACTV NOP READ
H
BA BA BA
ROW
ROW COL
t t
CAS latency
RP RCD
NOP PRE NOP ACTV NOP READ
H
BA BA BA
ROW
ROW COL
t t
CAS latency
RP RCD
NOP PRE NOP ACTV NOP READ NOP READ
H
BA BA BA
ROW
ROW COL1
t t
CAS latency
RP RCD
Figure 2.11 Burst Read in the Same Page
EPSON
= 2 cycles
RP
NOP
D(1) D(2) D(3) D(4) D(5) D(6)
= 2
NOP
D(1) D(2) D(3) D(4)
= 2
NOP
BA
COL2
D(1-1) D(1-2) D(2-1) D(2-2)
CAS latency
= 2 = 2
A-1
B-VI
SDRAM
B-VI-2-15