Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 69

Register name Address Bit
High-speed 0048230 DF
DMA Ch.1 (HW) DE
transfer DD
counter DC
register DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
High-speed 0048232 DF
DMA Ch.1 (HW) DE
control register
DD–8
Note:
D7
D) Dual address
D6
mode
D5
S) Single
D4
address
D3
mode
D2
D1
D0
High-speed 0048234 DF
DMA Ch.1 (HW) DE
low-order DD
source address DC
set-up register DB
DA
Note:
D9
D) Dual address
D8
mode
D7
S) Single
D6
address
D5
mode
D4
D3
D2
D1
D0
High-speed 0048236 DF
DMA Ch.1 (HW) DE
high-order DD
source address DC
set-up register
Note:
D) Dual address
DB
mode
DA
S) Single
D9
address
D8
mode
D7
D6
D5
D4
D3
D2
D1
D0
S1C33L03 PRODUCT PART
Name Function
TC1_L7 Ch.1 transfer counter[7:0]
TC1_L6 (block transfer mode)
TC1_L5
TC1_L4 Ch.1 transfer counter[15:8]
TC1_L3 (single/successive transfer mode)
TC1_L2
TC1_L1
TC1_L0
BLKLEN17 Ch.1 block length
BLKLEN16 (block transfer mode)
BLKLEN15
BLKLEN14 Ch.1 transfer counter[7:0]
BLKLEN13 (single/successive transfer mode)
BLKLEN12
BLKLEN11
BLKLEN10
DUALM1 Ch.1 address mode selection
D1DIR D) Invalid
S) Ch.1 transfer direction control
– reserved
TC1_H7 Ch.1 transfer counter[15:8]
TC1_H6 (block transfer mode)
TC1_H5
TC1_H4 Ch.1 transfer counter[23:16]
TC1_H3 (single/successive transfer mode)
TC1_H2
TC1_H1
TC1_H0
S1ADRL15 D) Ch.1 source address[15:0]
S1ADRL14 S) Ch.1 memory address[15:0]
S1ADRL13
S1ADRL12
S1ADRL11
S1ADRL10
S1ADRL9
S1ADRL8
S1ADRL7
S1ADRL6
S1ADRL5
S1ADRL4
S1ADRL3
S1ADRL2
S1ADRL1
S1ADRL0
– reserved
DATSIZE1 Ch.1 transfer data size
S1IN1 D) Ch.1 source address control
S1IN0 S) Ch.1 memory address control
S1ADRH11 D) Ch.1 source address[27:16]
S1ADRH10 S) Ch.1 memory address[27:16]
S1ADRH9
S1ADRH8
S1ADRH7
S1ADRH6
S1ADRH5
S1ADRH4
S1ADRH3
S1ADRH2
S1ADRH1
S1ADRH0
EPSON
4 PERIPHERAL CIRCUITS
Setting Init. R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1 Dual addr 0 Single addr 0
– –
1 Memory WR 0 Memory RD 0
– –
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
– –
1 Half word 0 Byte 0
S1IN[1:0] Inc/dec 0
1 1 Inc.(no init) 0
1 0 Inc.(init)
0 1 Dec.(no init)
0 0 Fixed
X
X
X
X
X
X
X
X
X
X
X
X
A-1
Remarks
R/W
A-4
R/W
R/W
–
R/W
– Undefined in read.
R/W
R/W
–
R/W
R/W
R/W
A-53