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II CORE BLOCK: ITC (Interrupt Controller)
Interrupt after IDMA transfer
To generate an interrupt after completion of IDMA transfer:
The interrupt request that has been kept pending can be generated after completion of the DMA transfer.
In this case, the interrupt must be enabled by the IDMA control information (DINTEM = "1") in adition to
the interrupt controller and the PSR register settings.
However, if the transfer counter set for the selected IDMA channel does not reach the terminal count of 0
after the number of transfers set have been performed, the interrupt factor flag is reset and no interrupt request
is generated. The transfer counter is decremented by 1 for each transfer performed.
If the transfer counter is decremented to 0 when DINTEN is set to "1", the interrupt factor flag is not reset
and the IDMA request bit is cleared to "0". An interrupt request is generated if other interrupt conditions are
met.
The IDMA request bit must be set up again in order for IDMA to be invoked when an interrupt factor occurs
next time as well. To ensure that no unwanted IDMA request occurs, this setup must be performed after
resetting the interrupt factor flag.
Figure 5.2 shows the hardware sequence when DINTEN is set to "1".
IDMA trigger (interrupt factor flag)
(reset interrupt factor flag)
(reset IDMA request bit)
To disable an interrupt after completion of IDMA transfer:
If an interrupt has been disabled in the IDMA control information (DINTEN = "0"), the interrupt is not
generated since the interrupt factor flag is reset when the transfer counter becomes 0.
In this case, the IDMA request bit remains set to "1" without being cleared. However, the IDMA enable bit is
cleared, so the following IDMA request by the same interrupt factor will be disabled.
Figure 5.3 shows the hardware sequence when DINTEN is set to "0".
IDMA trigger (interrupt factor flag)
(reset interrupt factor flag)
(reset IDMA request bit)
(reset IDMA enable bit)
For details on IDMA, refer to "IDMA (Intelligent DMA)".
B-II-5-10
Transfer counter
3
Data transfer
Reset A signal
Reset B signal
IDMA request bit
Figure 5.2 Sequence when DINTEN = "1"
Transfer counter
3
Data transfer
Reset A signal
Reset B signal
L
Reset C signal
IDMA request bit
"1"
IDMA enable bit
Figure 5.3 Sequence when DINTEN = "0"
2
1
2
1
EPSON
0
Interrupt request
0
S1C33L03 FUNCTION PART
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