Routing Illustration For Topology 1A; Routing Illustration For Topology 1B; Layout Recommendations For Topology 1A - Intel Pentium M Processor Design Manual

® ®
Intel Pentium M Processor and Intel
System Bus Routing Guidelines
Figure 27.

Routing Illustration for Topology 1A

Table 23.

Layout Recommendations for Topology 1A

L1
0.5" – 12.0"
5.1.7.1.2 Topology 1B: Open Drain (OD) Signals Driven by the Intel
FERR# and THERMTRIP#
The Topology 1B OD signals FERR# and THERMTRIP# should adhere to the following routing
and layout recommendations.
and THERMTRIP# signals of the Intel Pentium M processor. The routing guidelines allow signals
to be routed as either micro-strip or strip-line using 50 Ω ± 10% characteristic trace impedance.
Series resistor R1 is a dampening resistor for reducing overshoot/undershoot reflections on the
transmission line. The pull-up voltage for termination resistor R
It is recommended that the FERR# signal of the Intel Pentium M processor be routed to the FERR#
signal of the Intel ICH3-S. THERMTRIP# may be implemented in a number of ways to meet
design goals.
When either FERR# or THERMTRIP# is routed to an optional system receiver and the interface
voltage of the optional system receiver does not support a 1.05 V voltage swing, then a voltage
translation circuit must be used. When the recommended voltage translation circuit described in
Section 5.1.7.2, "Voltage Translation Logic"
Figure 32, R
to note that R1 may no longer be required in such a topology.
Figure 28.

Routing Illustration for Topology 1B

66
®
E7501 Chipset Platform
CPU
L2 L3
0" – 3.0" 0" – 3.0"
Table 24
, may replace the series dampening resistor R1 in Topology 1B. Thus, it is important
s
CPU
L1
System
Receiver
L2
R1
L1
R1 R
tt
56 Ω ± 5% 56 Ω ± 5%
lists the recommended routing requirements for the FERR#
tt
is used, the driver isolation resistor shown in
®
Intel
ICH3-S
(or sys. receiver)
L2
R1
VCCP
Rtt
L3
Transmission Line Type
Micro-strip and Strip-line
® ®
Pentium M Processor –
is V (1.05 V).
CCP
VCCP
Rtt
L3
Design Guide