Intel Pentium M Processor Design Manual page 5

7 Hub Interface.............................................................................................................................. 113
7.1 Signal Naming Convention ...............................................................................................113
7.2 Hub Interface 2.0 Implementation..................................................................................... 114
7.2.1 Hub Interface 2.0 High-Speed Routing Guidelines .............................................. 114
7.2.2 Hub Interface 2.0 Generation/Distribution of Reference Voltages ....................... 117
7.2.3 Hub Interface 2.0 Resistive Compensation.......................................................... 118
7.2.4 Hub Interface 2.0 Decoupling Guidelines ............................................................ 119
7.2.5 Unused Hub Interface 2.0 Interfaces ................................................................... 119
7.3 Hub Interface 1.5 Implementation..................................................................................... 120
7.3.1 Hub Interface 1.5 High-Speed Routing Guidelines .............................................. 120
7.3.2 Hub Interface 1.5 Generation/Distribution of Reference Voltages ....................... 121
7.3.3 Hub Interface 1.5 Resistive Compensation.......................................................... 122
7.3.4 Hub Interface 1.5 Decoupling Guidelines ............................................................ 122
®
8 Intel 82870P2 (Intel P64H2) ..................................................................................................... 123
8.1 PCI/PCI-X Design Guidelines ........................................................................................... 123
8.1.1 General PCI-X Routing Guidelines ...................................................................... 124
8.1.2 PCI/PCI-X Routing Requirements (No Hot-Plug Switch) ..................................... 125
8.1.3 PCI/PCI-X Hot-Plug Switch Routing Requirements .............................................125
8.1.4 Riser Card Topologies ......................................................................................... 126
8.1.5 PCI-X Two Devices Down-Routing Requirements............................................... 128
8.1.6 Clock Configuration ............................................................................................. 129
8.1.7 Loop Clock Configuration .................................................................................... 130
8.1.8 IDSEL Implementation ......................................................................................... 131
8.1.9 SMBus Address ................................................................................................... 131
8.2 Hot-Plug Implementation .................................................................................................. 132
8.2.1 Standard Usage Model ........................................................................................132
8.2.1.1
8.2.1.2
8.2.2 Hot-Plug Switch Implementation.......................................................................... 134
8.2.2.1
8.2.2.2
8.2.3 LED Indicator Outputs ......................................................................................... 135
8.2.4 Hot Plug Interrupt Routing Requirements ............................................................ 135
8.2.5 Hot-Plug Interrupt Routing Requirements............................................................ 136
8.2.6 Disabling/Enabling an Intel
8.2.6.1
8.2.6.2
8.2.7 Single-Slot Parallel Mode .................................................................................... 136
8.2.7.1
8.2.7.2
8.2.7.3
8.2.7.4
8.2.7.5
8.2.7.6
8.2.7.7
8.2.7.8
8.2.7.9
8.2.7.10 Reference Schematic for Single-Slot Parallel Mode ............................ 140
8.2.8 Dual-Slot Parallel Mode ....................................................................................... 141
8.2.8.1
Design Guide
® ®
Intel Pentium M Processor and Intel
Hot-Removals ...................................................................................... 133
Hot-Insertions....................................................................................... 133
Manually-Operated Retention Latch Sensor ........................................ 134
Optional Attention Button .....................................................................135
®
P64H2 Hot-Plug Controller..................................... 136
Hot-Plug Strapping Options ................................................................. 136
Hot-Plug Registers' Visibility ................................................................136
Required Additional Logic .................................................................... 136
PCI Clock ............................................................................................. 137
Debounced Hot-Plug Switch Input ....................................................... 137
Comparator Circuit for PCIXCAP1/PCIXCAP2 Pins ............................ 137
Tri-State Buffer or 2:1 Multiplexer for HPx_SLOT[2:0]......................... 137
Hot-Plug Multiplexed Signals in Single-Slot Parallel Mode .................. 138
SMBus Address Considerations .......................................................... 139
Single-Slot Parallel SMBus Circuit ....................................................... 140
Pull-Ups/Pull-Downs in Single-Slot Parallel Mode ...............................140
Required Additional Logic .................................................................... 141
®
E7501 Chipset Platform
Contents
5