Intel Pentium M Processor Design Manual page 12

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Intel Pentium M Processor and Intel
Contents
99 Reference Schematic for Single-Slot Parallel Mode................................................................. 141
100 Dual-Slot Parallel SMBus Circuit .............................................................................................. 144
101 Reference Schematic for Dual-Slot Parallel Mode ................................................................... 145
102 Four-Slot Stutter Logic Implementation Example ..................................................................... 147
103 Reference Schematic for Serial Mode ...................................................................................... 148
104 M66EN Isolation Switch Solution.............................................................................................. 150
105 M66EN Diode Solution ............................................................................................................. 151
106 Combination Host-Side/Device-Side IDE Cable Detection....................................................... 154
107 Connection Requirements for IDE Connector .......................................................................... 155
108 Example Speaker Circuit .......................................................................................................... 156
109 PCI Bus Layout Example.......................................................................................................... 157
110 Suggested USB Downstream Power Connection .................................................................... 159
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111 Intel ICH3-S SMBus / SMLink Interface ................................................................................. 160
112 Unified VCC3_3 Architecture.................................................................................................... 161
113 High Power/Low Power Mixed VCC_SUSPEND/ VCC_CORE Architecture ........................... 161
114 RTCX1 and SUSCLK Relationship........................................................................................... 163
115 RTC Connection When Not Using Internal RTC ...................................................................... 163
116 Example of RTC External Circuitry ........................................................................................... 164
117 Platform LAN Connect ............................................................................................................. 168
118 Point-to-Point Interconnect Guideline ....................................................................................... 169
119 LAN_CLK Routing Example ..................................................................................................... 170
120 Routing a 90-Degree Bend ....................................................................................................... 171
121 Ground Plane Separation ......................................................................................................... 172
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122 Intel 82562ET/Intel
123 Critical Dimensions for Component Placement ........................................................................ 176
124 Termination Plane .................................................................................................................... 178
125 ITP700FLEX Debug Port Signals ............................................................................................. 180
126 Processor Voltage Regulator Block Diagram ........................................................................... 188
127 Power Delivery Example .......................................................................................................... 189
128 Power On Sequencing Timing Diagram ................................................................................... 194
129 VCCP Block Diagram ............................................................................................................... 195
130 Voltage Regulator Multi-Phase Topology Example .................................................................. 197
131 Buck Voltage Regulator Example ............................................................................................. 197
132 High Current Path With Top MOSFET Turned ON................................................................... 198
133 High Current Path During Abrupt Load Current Changes ........................................................ 198
134 High Current Path With Top and Bottom MOSFETs Turned Off (Dead Time) ......................... 199
135 High Current Path With Bottom MOSFET(s) Turned ON ......................................................... 199
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136 Intel Pentium
137 MCH Decoupling (Backside View)............................................................................................ 204
138 Filter Topology for VCCA1_2 (DDR Interface) ......................................................................... 205
139 Filter Topology for VCCAHI1_2 (Hub Interface) ....................................................................... 206
140 Filter Topology for VCCACPU1_2 (E7501 System Bus) .......................................................... 206
141 Power Sequencing Requirement for MCH ............................................................................... 206
142 Sample 2.5 V Output Enable Control Logic .............................................................................. 207
143 Example 1.8 V/3.3 V Power Sequencing Circuit ...................................................................... 208
144 Another Example 1.8 V/3.3 V Power Sequencing Circuit ......................................................... 209
145 Example 3.3 V/V5REF Sequencing Circuitry ........................................................................... 209
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146 Intel P64H2 3.3 V PCI/PCI-X (V
147 Proper Decoupling Capacitor Placement with Respect to Vias ................................................ 216
148 Serpentine Routing ................................................................................................................... 217
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E7501 Chipset Platform
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82562EM Termination........................................................................... 176
M Processor GTLREF0 Voltage Divider Network .......................................... 203
) Capacitor Placement on Backside ........................... 213
CC_3.3
Design Guide