2.5 V Decoupling Requirements; Ddr Vterm Plane - Intel Pentium M Processor Design Manual

Figure 71.

DDR VTerm Plane

Two Vias Per 1 Capacitor
to the Internal Ground
1.25V Vterm Fill
One Rtt per signal
1.25V
Vterm Fill
Ground Fill
on Top Layer
50 mils
minimum
Two Vias Per 1
Capacitor to the
Internal Ground
Plane
6.4.9

2.5 V Decoupling Requirements

Decouple the DIMM connectors as shown in
(0603) capacitors between each pair of DIMM connectors. Place two Tantalum 100 µF capacitors
around each DIMM connector and two additional Tantalum 100 µF capacitors per channel, keeping
them within 0.5 inch of the DIMM connectors.
decoupling scheme and
Design Guide
®
Intel Pentium
Ground Fill on
Top Layer
Plane
Furthest DIMM from Intel
DIMM
Figure 73 depicts a single channel 4-DIMM decoupling scheme.
®
M Processor and Intel
Memory Interface Routing Guidelines
One 0.1 µF Decoupling
Capacitor per 2 Termination
Resistors or (2 Caps/Rpack)
0.5" max
®
MCH
DIMM
Figure 72 or Figure
Figure 72 depicts a single Channel 2-DIMM
®
E7501 Chipset Platform
50 mils
minimum
One 100 µF Tantalum
Capacitor at Each End
of Each Island
One 0.1 µF
decoupling
capacitor per 2
termination
resistors
73. Place six ceramic 0.1 µF
109