Example 1.8 V/3.3 V Power Sequencing Circuit - Intel Pentium M Processor Design Manual

® ®
Intel Pentium M Processor and Intel
Platform Power Delivery Guidelines
It is important to use 1% resistors for precise operating conditions in
doesn't overheat (junction temperature exceeds 125° C). Overheating could overdrive the 1.8 V rail
as high as 2 V.
Figure 143.

Example 1.8 V/3.3 V Power Sequencing Circuit

When analyzing systems that may be 'marginally compliant' to the Two Volt Rule, attention must
be paid to the behavior of the Intel ICH3-S's RSMRST# and PWROK signals because they control
internal isolation logic between the various power planes:
•
RSMRST# controls isolation between the RTC well and the resume wells.
•
PWROK controls isolation between the resume wells and main wells.
If one of these signals goes high while one of its associated power planes is active and the other is
not, a leakage path will exist between the active and inactive power wells. This could result in high,
possibly damaging, internal currents.
The circuit in
charge onto the 1.8 V rail at steady state. The circuit in
it is more susceptible to layout variations and should be fully analyzed and tested to make sure that
the implementation meets the 2 V specification. When choosing between the two circuits a
designer should understand the trade-offs with respect to their linear regulator design and
application.
The Semtech SC4431 monitors the difference between the reference pin (from 3.3 V) and the
ground pin (1.8 V). The SC4431 turns on its output when the difference between 1.8 V and 3.3 V is
over 1.9 V. Connecting the SC4431 ground pin to 1.8 V requires a series resistor from 1.8 V to
ground to complete the current path from the SC4431 VCC (5 VSB) to system ground. The series
resistor must be able to dissipate 0.25 W. This may be achieved using a 25 Ω resistor in a 1206
package, or two 51 Ω resistors in 0805 packages. The 1.8 V rail should be able to sink the current
from the SC4431 and the 1.13 k Ω / 2.05 k Ω divider.
208
®
E7501 Chipset Platform
+3.3V
220Ω ± 1%
Ω ± 1%
220
Q2
NPN
Ω ± 1%
470
Figure 144 may, under high temperature and parameter corner conditions, inject
Figure 143
+1.8V
Q1
PNP
Figure 143 does not have this characteristic;
to ensure the NPN
Design Guide