Dimm Types; Trace Width And Spacing For All Ddr Signals Except Cmdclk_X[3:0]/Cmdclk_X[3:0] - Intel Pentium M Processor Design Manual

Figure 34. Trace Width and Spacing for All DDR Signals Except CMDCLK_x[3:0]/
CMDCLK_x[3:0]#
Dielectric 3.8 mil
Dielectric 6.0 mil
Dielectric 20.0 mil
Dielectric 6.0 mil
Dielectric 3.8 mil
NOTE:
1. Traces on layers 5 and 6 must be routed orthogonally to each other to minimize the effects of crosstalk.
2. Trace width and spacing varies depending on the memory signal group. This chapter will detail the
requirements for all the memory signal groups.
6.2

DIMM Types

To allow flexibility in platform design this design guide supports three different DIMM connector
types: vertical, 25-degree and right-angle (see
DIMM connector type in the following sections.
Design Guide
®
Intel Pentium
Layer 1
Layer 2
Core 6.0 mil
Signal Layer 3
Layer 4
Core 3.8 mil
Signal
Layer 5
Layer 6
Signal
Core 3.8 mil
Layer 7
Signal
Layer 8
Core 6.0 mil
Layer 9
Layer 10
Trace Trace
Width Spacing
®
M Processor and Intel
Memory Interface Routing Guidelines
Signal
Dielectric
Ground
Core
Signal
Dielectric
Ground
Core
Signal
Main Dielectric
Signal
Core
Ground
Dielectric
Signal
Core
Ground
Dielectric
Signal
Trace Trace
Width Spacing
Figure 35). Routing guidelines are provided for each
®
E7501 Chipset Platform
2.1 mil (1 oz + plating)
1.2 mil (1 oz)
Signal
1.2 mil (1 oz)
1.2 mil (1 oz)
1.2 mil (1 oz)
Signal
1.2 mil (1 oz)
Signal
1.2 mil (1 oz)
1.2 mil (1 oz)
Signal
1.2 mil (1 oz)
2.1 mil (1 oz + plating)
Trace
Width
75