Embedded Pci-X 133 Mhz Alternate Topology; Embedded Pci-X 133 Mhz Alternate Topology Routing Recommendations - Intel 80331 Design Manual

Intel® 80331 I/O Processor Design Guide
PCI-X Layout Guidelines
6.4.4

Embedded PCI-X 133 MHz Alternate Topology

This section lists another embedded topology with routing recommendations for PCI-X 133 MHz.
Figure 19
recommendations.
Figure 19.

Embedded PCI-X 133 MHz Alternate Topology

Table 11.

Embedded PCI-X 133 MHz Alternate Topology Routing Recommendations

Parameter
Reference Plane
Preferred Layer
Break out
Motherboard impedance
(both Microstrip and stripline)
Add-in card impedance (both
Microstrip and stripline)
Stripline Trace Spacing
Microstrip Trace Spacing
Group Spacing
Trace Length 1 (TL1): From
80331 signal Ball to first
device
Trace Length 3 TL2: First
device to second device.
Length Matching
Requirements:
Number of vias
50
shows the block diagram of this topology and
Route over an unbroken ground plane
Stripline
5 mils on 5 mils spacing. Maximum length of breakout region is 500 mils
50 ohms +/- 15%
60 ohms +/- 15%
12 mils edge to edge
18 mils, edge to edge
Spacing from other groups: 25 mils minimum edge to edge
1.5" minimum - 3.5" maximum
1.5" minimum - 3.5" maximum
No length matching is required among datalines. For length matching for clocks,
refer clock guidelines
Three vias for each path
Table 11
EM1
TL1 TL2
Routing Guideline for Lower AD Bus
Table 8.
describes the routing
EM2