Intel Xeon Design Manual
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Intel Xeon Design Manual

Intel Xeon Design Manual

Processor and e7500/e7501 chipset compatible platform. addendum for embedded applications
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®
Intel
Xeon™ Processor and
®
Intel
E7500/E7501 Chipset
Compatible Platform
Design Guide Addendum for Embedded Applications
July 2003
Order Number: 273707-004

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Summary of Contents for Intel Xeon

  • Page 1 ® Intel Xeon™ Processor and ® Intel E7500/E7501 Chipset Compatible Platform Design Guide Addendum for Embedded Applications July 2003 Order Number: 273707-004...
  • Page 2 Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

  • Page 3: Table Of Contents

    Contents Contents Introduction............................7 Reference Documentation ....................7 Uni-processor System Bus Routing Guidelines................9 Routing Guidelines for the 2X and 4X Signal Groups............11 2.1.1 Design Recommendations..................12 Routing Guidelines for Common Clock Signals ..............13 2.2.1 Wired-OR Signals ....................13 Routing Guidelines for Asynchronous GTL+ and Miscellaneous Signals......14 2.3.1 Asynchronous GTL+ Signals Driven by the Processor..........15 2.3.1.1...
  • Page 4 Uni-processor System Bus Topology ..................10 Topology for Asynchronous GTL+ Signals Driven by the Processor.......... 15 ® FERR# Routing Topology for Low Voltage Intel Xeon™ Processors........16 Recommended THERMTRIP# Circuit ..................16 Topology for Asynchronous GTL+ Signals Driven by the Chipset..........17 INIT# Routing Topology for a Uni-processor System ..............
  • Page 5 22 DDRCVO Routing Guidelines.....................42 Revision History Date Revision Description Updated memory interface routing information and added Low July 2003 -004 ® Voltage Intel Xeon processor information. Updated and expanded memory interface routing information. January 2003 -003 Added E7501 chipset information. June 2002 -002...
  • Page 6 Contents This page intentionally left blank. Platform Design Guide Addendum...

  • Page 7: Introduction

    Xeon™ Processor and Intel E7500/E7501 http://developer.intel.com/design/chipsets/designex/ Chipset Compatible Platform Design Guide 251929.htm ® Intel Xeon™ Processor with 512 KB L2 Cache and http://developer.intel.com/design/chipsets/e7500/ Intel E7500 Chipset Platform Design Guide guides/298649.htm ® Intel Xeon™ Processor with 512 KB L2 Cache at http://developer.intel.com/design/Xeon/datashts/...
  • Page 8 ® Accuracy and Considerations Under Test Conditions 292276.htm http://developer.intel.com/design/Xeon/guides/ ITP700 Debug Port Design Guide 249679.htm ® Intel Xeon™ Processor with 512 KB L2 Cache Signal http://developer.intel.com/design/Xeon/devtools Integrity Models PCI Bus Power Management Interface Specification, http://www.pcisig.com/specifications/conventional/ Revision 1.1 pci_bus_power_management_interface http://www.pcisig.com/specifications/conventional/ PCI Hot Plug Specification, Revision 1.1 pci_hot_plug http://www.pcisig.com/specifications/conventional/...

  • Page 9: Uni-Processor System Bus Routing Guidelines

    6. Terminations and routing for TAP signals and all debug port signals are found in the ITP700 Debug Port Design Guide. 7. PROCHOT# is input/output on Low Voltage Intel® Xeon™ processor D-stepping and beyond. Platform Design Guide Addendum...

  • Page 10: Uni-Processor System Bus Topology

    Use this as a quick reference only. The following sections provide more information for each parameter. Intel strongly recommends simulation of all signals to ensure that setup and hold times are met. Table 3.

  • Page 11: Routing Guidelines For The 2X And 4X Signal Groups

    • Total bus length must not exceed 10”. • Trace length matching is required. Please contact your Intel field representative for a length matching spreadsheet. Trace length matching is required within each source synchronous group to compensate for the package trace length differences between data signals and the associated strobe. This will balance the strobe-to-signal skew in the middle of the setup and hold window.

  • Page 12: Design Recommendations

    ® ® Intel Xeon™ Processor and Intel E7500/E7501 Chipset Compatible Platform 2.1.1 Design Recommendations Below are the design recommendations for the data, address, strobes, and common clock signals. For the following discussion, the pad is defined as the attach point of the silicon pad to the package substrate.

  • Page 13: Routing Guidelines For Common Clock Signals

    The wired-OR signals should follow the same routing rules as the common clock signals. Intel recommends that simulations for these signals be performed for a given system.

  • Page 14: Routing Guidelines For Asynchronous Gtl+ And Miscellaneous Signals

    ® ® Intel Xeon™ Processor and Intel E7500/E7501 Chipset Compatible Platform Routing Guidelines for Asynchronous GTL+ and Miscellaneous Signals This section provides routing guidelines for the signals listed in Table Table 7. Asynchronous GTL+ and Miscellaneous Signals Signal Name Type...

  • Page 15: Asynchronous Gtl+ Signals Driven By The Processor

    A voltage translator circuit is required for the FERR# signal when VCC_CPU is less than 1.3 V, as ® it is for the Low Voltage Intel Xeon™ Processor. The required routing topology for FERR# is given in Figure Figure 6 shows the voltage translator circuit.

  • Page 16: Proper Thermtrip# Usage

    ® ® Intel Xeon™ Processor and Intel E7500/E7501 Chipset Compatible Platform ® Figure 3. FERR# Routing Topology for Low Voltage Intel Xeon™ Processors VCC_CPU VCC_CPU ICH3-S (FERR#) 56Ω 56Ω Processor Voltage Translator 3 inches max 1 to 12 inches 3 inches max...

  • Page 17: Asynchronous Gtl+ Signals Driven By The Chipset

    ® ® Intel Xeon™ Processor and Intel E7500/E7501 Chipset Compatible Platform 2.3.2 Asynchronous GTL+ Signals Driven by the Chipset Follow the topology shown in Figure 4 when routing A20M#, IGNNE#, INIT#, NMI, INTR, CPUSLP#, SMI#, STPCLK#, LINIT[1:0] and PWRGOOD. Figure 4. Topology for Asynchronous GTL+ Signals Driven by the Chipset VCC_CPU 200Ω...

  • Page 18: Br[3:0] Routing Guidelines For Uni-Processor Designs

    ® ® Intel Xeon™ Processor and Intel E7500/E7501 Chipset Compatible Platform Figure 5. INIT# Routing Topology for a Uni-processor System VCC_CPU 200Ω ® Intel Processor Voltage ICH3-S Translator 2 inches 3 inches max 1 to 12 inches This page intentionally left blank.

  • Page 19: Br[3:0]# Connection For Up Configuration

    ® ® Intel Xeon™ Processor and Intel E7500/E7501 Chipset Compatible Platform Figure 7. BR[3:0]# Connection for UP Configuration Processor VCC_CPU Rpu = RT = 50Ω ± 5% Note: A9049-01 Platform Design Guide Addendum...
  • Page 20 ® ® Intel Xeon™ Processor and Intel E7500/E7501 Chipset Compatible Platform Platform Design Guide Addendum...

  • Page 21: Memory Interface Routing Guidelines

    Dual channel configuration: The MCH consist of two DDR memory channels, channels A and B, that operate in ‘lock-step’. Each channel consists of 64 data and eight ECC bits. Logically, ® this is one, 144-bit wide memory bus; however, each channel is separate electrically. Intel E7500 supports only dual channel. •...

  • Page 22: Dimm Types

    The letters ‘A’ and ‘B’ in the DIMM figure refer to the DIMM channel. The number following ‘A’ or ‘B’ refers to the DIMM logical group. The DIMMs are physically interleaved. Intel recommends using this ordering, starting with Channel B closest to the MCH, for optimal routing.

  • Page 23: Dual Channel Source Synchronous Signal Group Routing

    Dual Channel Source Synchronous Signal Group Routing Table 8 states the routing requirements for the DQ, DQS and CB signals. All signals in a data group ® must be length matched to the associated DQSs, as described in the Intel Xeon™ Processor and ® Intel E7500/E7501 Chipset Compatible Platform Design Guide.

  • Page 24: Dual Channel Source Synchronous Signal Group Routing Guidelines

    1. The DQS pair in the group must also be tuned to each other with this parameter. The DQ and DQS lines in the same group must be length tuned to all DIMMs. Tune all lengths to the Intel E7501 chipset MCH package trace lengths.

  • Page 25: Dual Channel Command Clock Routing

    ® ® Intel Xeon™ Processor and Intel E7500/E7501 Chipset Compatible Platform 3.2.2 Dual Channel Command Clock Routing Only one differential clock pair is routed to each DIMM connector because the MCH only supports registered DDR DIMMs. All CMDCLK/CMDCLK# termination is on the DIMM modules. Route each clock and its compliment adjacent to each other.

  • Page 26: Dual Channel Source Clocked Signal Group Routing

    ® ® Intel Xeon™ Processor and Intel E7500/E7501 Chipset Compatible Platform Figure 11. Dual Channel 2-DIMM Command Clock Topology A_CMDCLK0 & CMDCLK0# Channel A A_CMDCLK1 & CMDCLK1# B_CMDCLK0 & CMDCLK0# Channel B B_CMDCLK1 & CMDCLK1# DIMMs NOTES: 1. CMDCLK/CMDCLK# must be matched to within ± 2 mils using package trace length compensation.

  • Page 27: Dual Channel Chip Select Routing

    ® ® Intel Xeon™ Processor and Intel E7500/E7501 Chipset Compatible Platform 3.2.4 Dual Channel Chip Select Routing The MCH provides eight chip select signals. Two chip selects must be routed to each DIMM (one for each side). Chip selects for each DIMM must be length matched to the corresponding clock within ±...

  • Page 28: Dual Channel Clock Enable Routing

    ® ® Intel Xeon™ Processor and Intel E7500/E7501 Chipset Compatible Platform 3.2.5 Dual Channel Clock Enable Routing The MCH provides a single clock enable (CKE) signal. This signal is used during initialization to indicate that valid power and clocks are being applied to the DIMMs. Because the CKE signal has higher loading, it requires a lower impedance.

  • Page 29: Dimm Per Channel Decoupling

    ® ® Intel Xeon™ Processor and Intel E7500/E7501 Chipset Compatible Platform Figure 12. 1-DIMM Per Channel Decoupling 8 Tantulum 100 µF Capacitors Around The DIMMs DIMM DIMM 2 Vias Per Capacitor to 6 Ceramic 0.10 µF Caps Internal Ground Plane...

  • Page 30: Single Channel Ddr Overview

    Figure 15). This recommendation is based on the signal integrity requirements of the DDR interface. Intel’s recommendation is to check for correct DIMM placement during BIOS initialization. Additionally, it is strongly recommended that all designs follow the DIMM ordering, SMBus Addressing, Command Clock...

  • Page 31: Unused Channel B

    ® ® Intel Xeon™ Processor and Intel E7500/E7501 Chipset Compatible Platform Single Channel routing guidelines listed in the following sections are described for one or two DIMMs. When single channel three or four DIMMs guidelines are needed, follow the dual channel guidelines for three or four DIMMs listed in Section 3.2, “Dual Channel DDR...

  • Page 32: Single Channel Source Synchronous Signal Group Routing

    ® ® Intel Xeon™ Processor and Intel E7500/E7501 Chipset Compatible Platform Table 13. Channel B Signal Terminations Signal Name Single Channel PCB Recommended Connection Bidirectional Signal Group 47 Ω +- 1% pullup to DDR Vterm (1.25 V). See CB_B[7:0] Section 3.3.2 47 Ω...
  • Page 33 In x8 configurations, only the low DQS is used. Table 15 states the routing requirements for the DQ, DQS and CB signals. All signals in a data ® group must be length matched to the associated DQSs, as described in the Intel Xeon™ Processor ® and Intel E7500/E7501 Chipset Compatible Platform Design Guide.

  • Page 34: Single Channel Source Synchronous Signal Group Routing Guidelines

    1. The DQS pair in the group must also be tuned to each other with this parameter. The DQ and DQS lines in the same group must be length tuned to all DIMMs. Tune all lengths to the Intel E7501 chipset MCH package trace lengths.

  • Page 35: Single Channel Source Synchronous Topology Dimm Solution

    ® ® Intel Xeon™ Processor and Intel E7500/E7501 Chipset Compatible Platform Figure 16. Single Channel Source Synchronous Topology DIMM Solution DDR VTERM (1.25V) DQ/CB Data Group Channel A Associated DQS Rs to DIMM to DIMM DIMM1 DIMM to Rtt MCH to DIMM1...

  • Page 36: Single Channel Command Clock Routing

    ® ® Intel Xeon™ Processor and Intel E7500/E7501 Chipset Compatible Platform 3.3.3 Single Channel Command Clock Routing Only one differential clock pair is routed to each DIMM connector because the MCH only supports registered DDR DIMMs. All CMDCLK/CMDCLK# termination is on the DIMM modules. Route each clock and its compliment adjacent to each other.

  • Page 37: Single Channel Source Clocked Signal Group Routing

    ® ® Intel Xeon™ Processor and Intel E7500/E7501 Chipset Compatible Platform 3.3.4 Single Channel Source Clocked Signal Group Routing The MCH drives the command clock signals and the source-clocked signals together. That is, the MCH drives the command clock in the center of the valid window, and the source-clocked signals propagate with the command clock signal.

  • Page 38: Single Channel Chip Select Routing

    ® ® Intel Xeon™ Processor and Intel E7500/E7501 Chipset Compatible Platform 3.3.5 Single Channel Chip Select Routing The MCH provides eight chip select signals. Two chip selects must be routed to each DIMM (one for each side). Chip selects for each DIMM must be length matched to the corresponding clock within ±...

  • Page 39: Single Channel Clock Enable Routing

    ® ® Intel Xeon™ Processor and Intel E7500/E7501 Chipset Compatible Platform 3.3.6 Single Channel Clock Enable Routing The MCH provides a single clock enable (CKE) signal. This signal is used during initialization to indicate that valid power and clocks are being applied to the DIMMs. Because the CKE signal has higher loading, it requires a lower impedance.

  • Page 40: Single Channel Dc Biasing Signals

    The DC Biasing signals are DDR signals which are not channel configuration specific. The following sections describe the DC Biasing signals. 3.3.7.1 Single Channel Receive Enable Signal (RCVEN#) The Intel E7501 chipset MCH requires a pull-up resistor (Rtt) to DDR VTERM on RCVEN. Table 20 lists the guidelines. Figure 22 summarizes these options.

  • Page 41: Single Channel Ddrcomp

    The MCH uses DDRCOMP_A to calibrate the DDR channel buffers. This is periodically done by sampling the DDRCOMP pin on the MCH. The Intel E7501 chipset MCH calibrates using a 24.9 Ω ± 1% pull-down to ground. This may be implemented by routing a 15 mils wide trace to a...

  • Page 42: Single Channel Ddr Signal Termination And Decoupling

    Ω ± 1% 1 nF 3.3.8 Single Channel DDR Signal Termination and Decoupling ® ® Follow design guidelines provided in the Intel Xeon™ Processor and Intel E7500/E7501 Chipset Compatible Platform Design Guide. 3.3.9 2.5 V Decoupling Requirements Decouple the DIMM connectors as shown in...

  • Page 43: Single Channel 2-Dimm Decoupling

    ® ® Intel Xeon™ Processor and Intel E7500/E7501 Chipset Compatible Platform Figure 25. Single Channel 2-DIMM Decoupling 8 Tantulum 100 µF Capacitors Around The DIMMs DIMM DIMM 2 Vias Per Capacitor to 6 Ceramic 0.10 µF Caps Internal Ground Plane...

  • Page 44: Single Channel 4-Dimm Decoupling

    ® ® Intel Xeon™ Processor and Intel E7500/E7501 Chipset Compatible Platform Figure 26. Single Channel 4-DIMM Decoupling 12 Tantulum 100 µF Capacitors Around The DIMMs DIMM DIMM DIMM DIMM 2 Vias Per Capacitor to 6 Ceramic 0.10 µF Caps Internal Ground Plane...

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E7500E7501

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