Single Channel 4-Dimm Implementation; Example Of Proper Single Channel Rank Mixing - Intel Pentium M Processor Design Manual

Figure 56.

Single Channel 4-DIMM Implementation

Certain combinations of DIMM types in 3-DIMM and 4-DIMM per channel systems have been
found to violate the JEDEC write ring back measurement specification. 1-DIMM and 2-DIMM per
channel systems do not violate the JEDEC write ring back specification. When combining
double-rank DIMMs (x4 or x8) with single-rank DIMMs (x4 or x8), if the first populated slot
(closest to the MCH) contains a single-ranked DIMM, the write ringback at that DIMM violates the
JEDEC DRAM specification (see
DIMMs furthest from the MCH when a combination of single-ranked and double-ranked DIMMs
is used (see
To determine if a registered DDR DIMM is a single-bank DIMM or a double-bank DIMM, refer to
Distinguishing Between Single-Rank and Double-Rank Registered DDR DIMM Modules
Application Note (AP-727) or contact your Intel representative for more information.
Figure 57.

Example of Proper Single Channel Rank Mixing

Design Guide
®
Intel Pentium
M C H
SM Bu s A dd ress:
C om m a nd C lock:
C hip Se le ct:
Figure
Figure 57).
MCH
®
M Processor and Intel
Memory Interface Routing Guidelines
D u al R a nked D IM M s
F ill S eco nd
D D D
I I
M M M
M M M
A1 A 2 A3
0 0h 0 1h 02 h
0 /0# 1 /1 # 2/2#
0/1 2/3 4 /5
58). To reduce write ring back, populate single-ranked
®
E7501 Chipset Platform
Sing le R an ked D IM M s
Fill F irst
F ill First
D
I I
M
M
A4
0 3h
3 /3 #
6/7
95