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4.3
CLK66 Clock Group
In the CLK66 clock group, the driver is the clock synthesizer 66 MHz clock output buffer, and the
receiver is the 66 MHz clock input buffer at the MCH, Intel ICH3-S, and Intel
Figure 12.
Topology for CLK66
Table 8.
CLK66 Routing Guidelines
Clock Group
Topology
Reference Plane
Characteristic Trace Impedance (Z
Trace Width
Trace Spacing
Trace Length – L1
Trace Length – L2
Resistor
Skew Requirements
Clock Driver to MCH
Clock Driver to Intel
Clock Driver to Intel
NOTES:
1. For better understanding of the concept, refer to
and
Figure
2. Assuming no connector.
3. All trace width and spacing recommendations are derived from a target impedance and crosstalk
sensitivity. This is based upon the stackup defined in
simulated.
Design Guide
®
Intel
Pentium
L1
Clock
Driver
Parameters
)
0
3
3
®
ICH3-S
®
P64H2
14.
®
M Processor and Intel
Platform Clock Routing Guidelines
L2
R1
Routing Guidelines
CLK66
Point-to-Point
Ground referenced (contiguous over entire length)
50 Ω ± 10%
5 mils
25 mils
0.00 – 0.50"
3.00 – 9.00"
±
R1 = 43 Ω
5%
All the clocks in the CLK66 group must have < 100-mils skew
between each other.
1
"
X = (3.0 – 9.5
)
, where X = L1 + L2
1
X = (3.0 – 9.5")
, where X = L1 + L2
2
X – 0.34"
, where X = L1 + L2
Section 4.3.1, "CLK66 Skew
Section
3.1. Any deviation from this stackup must be
®
E7501 Chipset Platform
®
P64H2.
MCH,
®
Intel
ICH3-S,
®
Intel
P64H2
Requirements",
Figure 13
47
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