Loop Clock Configuration; No Hot-Plug Clock Topology; Loop Clock Topology - Intel Pentium M Processor Design Manual

® ®
Intel Pentium M Processor and Intel
®
Intel 82870P2 (Intel P64H2)
Figure 91.

No Hot-Plug Clock Topology

Table 71. No Hot-Plug Clock Routing Length Parameters
Clock Speed
33 MHz Slot
66 MHz
100 MHz
133 MHz
1. The clock signal and feedback loops are closely related. L2 and L
tuned to each other ± 25 mils. Refer to
8.1.7

Loop Clock Configuration

You must tie PxPCLKO6 to PxPCLKI because this clock always runs and is needed by the internal
PCI PLLs to properly align output signals with the external clocks by removing clock insertion
delay. The PxPCLKO6 signal does not have to be routed through a bus switch before returning to
PxPCLKI.
Figure 92.

Loop Clock Topology

130
®
E7501 Chipset Platform
®
Intel
P64H2
L1 (inches)
3.5 – 5.5
3.5 – 4.5
≤ 1.0
≤ 1.0
PxPCLKO6
®
Intel
P64H2
PxPCLKI
Ω
L1 33
L2 (inches) Slot
0.5 – 5.0
0.5 – 1.0
1
L – 2.5
fbi
1
L – 2.5
fbi
fbi
Figure 91 for L2, and Figure 92
L
fbo
L
fbi
Slot or
Device Down
L2
L2 (inches) Device Down
2.9 – 7.9
3.0 – 3.5
1
L
fbi
1
L
fb
may be any length, but need to be
for L .
fbi
33 Ω
Design Guide