Intel ® Ich3-S Layout Checklist - Intel Pentium M Processor Design Manual

®
14.3 Intel
®
Table 102. Intel ICH3-S Layout Checklist (Sheet 1 of 4)
Checklist Items
A20M#
CPUSLP#
FERR#
IGNNE#
INIT#
LINT[1:0]
SMI#
STPCLK#
Decoupling
General Guidelines
General Guidelines
Design Guide
®
Intel Pentium
ICH3-S Layout Checklist
Recommendations
See processor section of this checklist.
• 0.1 µF capacitors should be placed
between the VCC supply balls and the
VSS ground balls. The capacitors
should be within 390 mils from the VCC
supply balls.
• 4.7 µF capacitors should be placed
between the VCC supply balls and the
VSS ground balls, and no less than 390
mils from the VCC supply balls.
Hub Interface - See MCH section
• Traces are routed 5 mils wide with 7
mils spacing.
• Max trace length is eight inches long.
• The maximum length difference
between the longest and shortest trace
length is 0.5 inches.
Traces: 5 mils wide, 10 mils spacing.
LAN Max Trace Length ICH3-S to CNR:
L = Three inches to nine inches (0.5 inch to
three inches on card).
Stubs due to R-pak CNR/LOM stuffing
option should not be present.
Maximum Trace Lengths:
®
• Intel ICH3-S to Intel
L = 4.5 inches to 10 inches.
®
• Intel 82562ET: L = 3.5 inches to ten
inches
®
• Intel 82562EM: L = 3.5 inches to ten
inches
Maximum mismatch between the length of
a clock trace and the length of any data
trace is 0.5 inch (clock must be the longest
trace).
®
M Processor and Intel
Processor Signals
FWH Interface
IDE Checklist
• Refer to ATA ATAPI-4 specification.
• Refer to
LAN Interface
Refer to
To meet timing requirements.
To minimize inductance.
®
82562EH:
To meet timing requirements.
To meet timing and signal quality
requirements.
®
E7501 Chipset Platform
Layout Checklist
Comments
Section 9.1.3.
Section 9.7.
275