Source Synchronous - Address; Data Signal Routing Guidelines; Intel ® Pentium ® M Processor System Bus Address Source Synchronous; Signal Trace Length Mismatch Mapping - Intel Pentium M Processor Design Manual

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Table 19. Intel Pentium

Data Signal Routing Guidelines

CPU
DINV[3:0]#
D[63:0]#
DSTBN[3:0]#
DSTBP[3:0]#
5.1.5.3 Source Synchronous – Address
Source synchronous address signals operate at 200 MHz. Thus, their routing requirements are very
similar to the data signals. Refer to
Guidelines"
the partition of the address signals into matched length groups. Due to the lower operating
frequency of the address signals, pad-to-pad length matching is relaxed to ± 200 mils. Each group
is associated with only one strobe signal. To maximize setup/hold time margin, the address strobes
should be trace length-matched to the average trace length of the address signals of their associated
group. In addition, each address signal should be trace length-matched within ± 200 mils of its
associated strobe signal.
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Table 20. Intel Pentium

Signal Trace Length Mismatch Mapping

CPU Signal Name
REQ[4:0]#, A[16:3]#
A[31:17]#
† ADSTB[1:0]# should be should be trace length-matched to the average length of their associated address
signals group.
Table 21
MHz, high frequency operation of the address signals, they must maintain a 1:3 spacing and trace
lengths should be limited to a pad-to-pad trace length minimum of 3.0 inch and a maximum of 7.5
inches. The routing guidelines listed in
given a 50 Ω ± 10% characteristic trace impedance. For the address strobes, 1:3 spacing is also
required irrespective of the tolerance of the trace impedance.
Design Guide
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Intel Pentium
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M Processor System Bus Source Synchronous
Signal Names
MCH
DBI[3:0]#
HD[63:0]#
HDSTBN[3:0]#
HDSTBP[3:0]#
and Section 5.1.5.2, "Source Synchronous – Data"
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M Processor System Bus Address Source Synchronous
Signal Matching
± 200 mils
± 200 mils
lists the source synchronous address signals general routing requirements. Due to the 200
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M Processor and Intel
System Bus Routing Guidelines
Total Trace Length
Transmission
Line Type
Min
(inches)
Strip-line 3.0
Section 5.1.5.1, "Source Synchronous General Routing
Strobe Associated with the
Group
ADSTB0#
ADSTB1#
Table 21 shows the 1:3 spacing for the address signals
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E7501 Chipset Platform
Normal Width and
Impedance
Max
(Ω)
(inches)
7.5 50 ± 10% 5 and 15
for further details. Table 20
Strobe to
Associated
Address Signal
Matching
± 200 mils
± 200 mils
spacing
(mils)
details
Notes
†
†
63