Intel Pentium II Developer's Manual
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Intel Pentium II Developer's Manual

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Pentium
II Processor
Developer's Manual
243502-001
October 1997
1997

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  • Page 1 ® Pentium II Processor Developer’s Manual 243502-001 October 1997 1997...
  • Page 2 Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

  • Page 3: Table Of Contents

    TABLE OF CONTENTS CHAPTER 1 COMPONENT INTRODUCTION 1.1. SYSTEM OVERVIEW....................1-1 1.2. TERMINOLOGY...................... 1-2 1.2.1. S.E.C. Cartridge Terminology ................1-3 1.3. REFERENCES ......................1-3 CHAPTER 2 MICRO-ARCHITECTURE OVERVIEW 2.1. FULL CORE UTILIZATION..................2-2 THE PENTIUM ® II PROCESSOR PIPELINE ............2-3 2.2.
  • Page 4 CONTENTS 4.2.3. Unprotected Bus Signals..................4-3 4.2.4. Hard-Error Response................... 4-4 Pentium ® II Processor System Bus Error Code Algorithms ........4-4 4.2.5. 4.2.5.1. PARITY ALGORITHM..................4-4 PENTIUM ® II SYSTEM BUS ECC ALGORITHM..........4-4 4.2.5.2. CHAPTER 5 CONFIGURATION 5.1. DESCRIPTION......................5-1 5.1.1.
  • Page 5 CONTENTS 7.2.1. Normal State — State 1..................7-3 7.2.2. Auto HALT Power Down State — State 2............. 7-3 7.2.3. Stop-Grant State — State 3 ................. 7-3 7.2.4. HALT/Grant Snoop State — State 4..............7-4 7.2.5. Sleep State — State 5 ..................7-4 7.2.6.
  • Page 6 CONTENTS CHAPTER 10 THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS 10.1. THERMAL SPECIFICATIONS ................10-1 PENTIUM ® II PROCESSOR THERMAL ANALYSIS ..........10-2 10.2. 10.2.1. Thermal Solution Performance................10-2 10.2.2. Measurements for Thermal Specifications............10-3 10.2.2.1. THERMAL PLATE TEMPERATURE MEASUREMENT ........10-3 10.2.2.2. COVER TEMPERATURE MEASUREMENT ............10-5 10.3.
  • Page 7 CONTENTS CHAPTER 14 ADVANCED FEATURES 14.1. ADDITIONAL INFORMATION ................14-1 APPENDIX A SIGNALS REFERENCE Figures Figure Title Page 1-1. Second Level Cache Implementations ..............1-2 2-1. Three Engines Communicating Using an Instruction Pool........2-1 2-2. A Typical Pseudo Code Fragment................ 2-2 2-3.
  • Page 8 CONTENTS 8-11. Standard Input Lo-to-Hi Waveform for Characterizing Receiver Setup Time ..8-17 8-12. Standard Input Hi-to-Lo Waveform for Characterizing Receiver Setup Time ..8-18 9-1. BCLK, TCK PICCLK Generic Clock Waveform at the Processor Edge Fingers ..9-2 9-2. Non-GTL+ Overshoot/Undershoot and Ringback Tolerance ......... 9-4 10-1.
  • Page 9 CONTENTS Pentium ® II Processor Integration Tool Mechanical Keep Out Volume— 13-13. Side View ......................13-15 A-1. PWRGOOD Relationship at Power-On............... A-11 Tables Table Title Page Pentium ® II Processor Execution Unit Pipelines..........2-13 2-1. 3-1. Execution Control Signals ..................3-2 3-2. Arbitration Signals....................
  • Page 10 CONTENTS 8-4. I/O Buffer AC Parameters...................8-14 9-1. BCLK Signal Quality Specifications ..............9-1 9-2. GTL+ Signal Groups Ringback Tolerance ............9-3 9-3. Signal Ringback Specifications for Non-GTL+ Signals .......... 9-5 Pentium ® II Processor Thermal Design Specifications (1) ........10-2 10-1. Example Thermal Solution Performance for 266 MHz Pentium ®...

  • Page 11: Component Introduction

    Component Introduction...

  • Page 13: System Overview

    II processor is the next in the Intel386™, Intel486™, Pentium and Pentium Pro line of Intel processors. The Pentium II and Pentium Pro processors are members of the P6 family of processors, which includes all of the Intel Architecture processors that implement Intel’s dynamic execution micro-architecture.

  • Page 14: Terminology

    Processor Core Schematic only ® Pentium Pro Processor Pentium II Processor Dual Die Cavity Package Substrate and Components 000756c Figure 1-1. Second Level Cache Implementations The S.E.C. cartridge has the following features: a thermal plate, a cover and a substrate with an edge finger connection.

  • Page 15: Cartridge Terminology

    1.3. REFERENCES The reader of this specification should also be familiar with material and concepts presented in the following documents: • AP-485, Intel Processor Identification with the CPUID Instruction (Order Number 241618) • ® AP-585, Pentium II Processor GTL+ Guidelines (Order Number 243330) •...
  • Page 16 ® Pentium II Processor I/O Buffer Models, IBIS Format (Electronic Form) • Intel Architecture Software Developer’s Manual Volume I: Basic Architecture (Order Number 243190) Volume II: Instruction Set Reference (Order Number 243191) Volume III: System Programming Guide (Order Number 243192)

  • Page 17: Micro-Architecture Overview

    Micro-Architecture Overview...

  • Page 19: Three Engines Communicating Using An Instruction Pool

    The Pentium II processor, for example, has twelve stages with a pipestage time 33 percent less than the Pentium processor, which helps achieve a higher clock rate on any given manufacturing process.

  • Page 20: Full Core Utilization

    The sparse register set of an Intel Architecture (IA) processor will create many false dependencies on registers so the dispatch/execute unit will rename the Intel Architecture registers into a larger register set to enable additional forward progress.

  • Page 21: The Pentium ® Ii Processor Pipeline

    In order to get a closer look at how the P6 family micro-architecture implements Dynamic Execution, Figure 2-3 shows a block diagram of the Pentium II processor with cache and memory interfaces. The “Units” shown in Figure 2 represent stages of the Pentium II processor pipeline.

  • Page 22: The Fetch/Decode Unit

    Intel Architecture instructions are marked. Three parallel decoders accept this stream of marked bytes, and proceed to find and decode the Intel Architecture instructions contained therein. The decoder converts the Intel Architecture instructions into triadic µops (two logical sources, one logical destination per...

  • Page 23: The Dispatch/Execute Unit

    MICRO-ARCHITECTURE OVERVIEW µop). Most Intel Architecture instructions are converted directly into single µops, some instructions are decoded into one-to-four µops and the complex instructions require microcode (the box labeled Microcode Instruction Sequencer in Figure 2-4). This microcode is just a set of preprogrammed sequences of normal µops. The µops are queued, and sent to...

  • Page 24: The Retire Unit

    MICRO-ARCHITECTURE OVERVIEW The Pentium II processor can schedule at a peak rate of 5 µops per clock, one to each resource port, but a sustained rate of 3 µops per clock is more typical. The activity of this scheduling process is the out-of-order process; µops are dispatched to the execution resources strictly according to dataflow constraints and resource availability, without regard to the original ordering of the program.

  • Page 25: The Bus Interface Unit

    µops that have executed and can be removed from the pool. Once removed, the original architectural target of the µops is written as per the original Intel Architecture instruction. The Retire Unit must not only notice which µops are complete, it must also re-impose the original program order on them.

  • Page 26: Inside The Bus Interface Unit

    MICRO-ARCHITECTURE OVERVIEW System Memory Memory Order Buffer Memory L2 Cache DCache From Address To/From Generation Unit Instruction Pool (ReOrder Buffer) 000930 Figure 2-7. Inside the Bus Interface Unit There are two types of memory access: loads and stores. Loads only need to specify the memory address to be accessed, the width of the data being retrieved, and the destination register.

  • Page 27: Mmx™ Technology And The Pentium ® Ii Processor

    Long latency operations can proceed in parallel with short latency operations. The Pentium II pipeline is comprised of three parts: (1) the In-Order Issue Front-end, (2) the Out-of-Order Core, and the (3) In-Order Retirement unit. Details about the In-Order Issue Front-end follow below.

  • Page 28: Out Of Order Core And Retirement Pipeline

    MICRO-ARCHITECTURE OVERVIEW BTB0 BTB1 IFU0 IFU: Instruction Cache Unit IFU1 IFU1: In this stage, 16-byte instruction packets are fetched. The packets are aligned on 16-byte boundaries. IFU2 IFU2: Instruction Pre-decode: double buffered: 16-byte packets aligned on any boundary. ID0: Instruction Decode ID1: Decode 1 stage: decoder limits = at most 3 macro-instructions per cycle...
  • Page 29 2. Up to six µops per clock cycle. 3. Macro-instructions up to seven bytes in length. Pentium II processors have three decoders in the D1 pipestage. The first decoder is capable of decoding one Intel Architecture macro-instruction of four or fewer µops in each clock cycle.

  • Page 30: Additional Information

    MICRO-ARCHITECTURE OVERVIEW Reservation station (RS): A µop can remain in the RS for many cycles or simply move past to an execution unit. On average, a µop will remain in the RS for three cycles or pipestages. Execution pipelines coming out of the RS are multiple pipelines grouped into five clusters.

  • Page 31: Caches

    MICRO-ARCHITECTURE OVERVIEW Table 2-1. Pentium ® II Processor Execution Unit Pipelines Port Execution Unit Latency/Throughput Notes Integer ALU Unit Latency 1, Throughput 1/cycle LEA instructions Latency 1, Throughput 1/cycle Shift Instructions Latency 1, Throughput 1/cycle Integer Multiplication instruction Latency 4, Throughput 1/cycle Floating-Point Unit Latency 3, Throughput 1/cycle FADD instruction...

  • Page 32: Write Buffers

    The data cache consists of eight banks interleaved on four-byte boundaries. On the Pentium II processors, the data cache can be accessed simultaneously by a load instruction and a store instruction, as long as the references are to different cache banks. On Pentium II processors the minimum delay is ten internal clock cycles.

  • Page 33: System Bus Overview

    System Bus Overview...

  • Page 35: Latched Bus Protocol

    This chapter provides an overview of the Pentium II processor system bus, bus transactions, and bus signals. The Pentium II processor system bus is based on the P6 Family system bus architecture, which is also implemented in the Pentium Pro processor. The Pentium II...

  • Page 36: Signal Overview

    SYSTEM BUS OVERVIEW The square and circle symbols are used in the timing diagrams to indicate the clock in which particular signals of interest are driven and sampled. The square indicates that a signal is driven (asserted, initiated) in that clock. The circle indicates that a signal is sampled (observed, latched) in that clock.

  • Page 37: Arbitration Signals

    RESET#, then the processor tristates all of its outputs. This function is used during board testing. The Pentium II processor supplies a STPCLK# pin to enable the processor to enter a low power state. When STPCLK# is asserted, the processor puts itself into the Stop-Grant state.

  • Page 38: Arbitration Signals

    SYSTEM BUS OVERVIEW Table 3-2. Arbitration Signals Pin/Signal Name Pin Mnemonic Signal Mnemonic Symmetric Agent Bus Request BR[1:0]# BREQ[1:0]# Priority Agent Bus Request BPRI# BPRI# Block Next Request BNR# BNR# Lock LOCK# LOCK# The symmetric agents arbitrate for the bus based on a round-robin rotating priority scheme. The arbitration is fair and symmetric.

  • Page 39: Request Signals

    RP# and AP[1:0]# signals are valid in the clock that ADS# is asserted. In the clock that ADS# is asserted, the A[35:3]# signals provide a 36-bit, active-low address as part of the request. The Pentium II processor physical address space is 2 bytes or 64- gigabits (64 GByte).

  • Page 40: Response Signals

    SYSTEM BUS OVERVIEW On observing a transaction, HIT# and HITM# are used to indicate that the line is valid or invalid in the snooping agent, whether the line is in the modified (dirty) state in the caching agent, or whether the transaction needs to be extended. The HIT# and HITM# signals are used to maintain cache coherency at the system level.

  • Page 41: Data Response Signals

    The DEP[7:0]# signals provide optional ECC (error correcting code) covering D[63:0]#. As described in Chapter 5, Configuration, the Pentium II data bus can be configured with either no checking or ECC. If ECC is enabled, then DEP[7:0]# provides valid ECC for the entire data bus on each data clock, regardless of which bytes are enabled.
  • Page 42 (see Chapter 5, Configuration). If the BINIT# driver is disabled, BINIT# is never asserted and no action is taken on bus errors. Regardless of whether the BINIT# driver is enabled, the Pentium II processor supports two modes of operation that may be configured at power on. These are the BINIT# observation and driving modes.

  • Page 43: Compatibility Signals

    20 clocks and then deasserts it. 3.2.8. Compatibility Signals The compatibility signals group (see Table 3-8) contains signals defined for compatibility within the Intel Architecture processor family. Table 3-8. PC Compatibility Signals Type Signal Names Floating-Point Error...

  • Page 44: Diagnostic Signals

    SYSTEM BUS OVERVIEW The A20M# and IGNNE# signals have different meanings during a reset. A20M# and IGNNE# are sampled on the active to inactive transition of RESET# to determine the multiplier for the internal clock frequency, as described in Chapter 5, Configuration. System Management Interrupt is asserted asynchronously by system logic.

  • Page 45: Data Integrity

    Data Integrity...

  • Page 47: Error Classification

    Unrecoverable errors cause the INT 18 machine check exception, as in the Pentium Pro processor. If machine check is disabled, or an error occurs in a Pentium II processor system bus agent without the machine check architecture, the Pentium II processor system bus defines a bus error reporting mechanism.

  • Page 48: Bus Signals Protected Directly

    II PROCESSOR SYSTEM BUS DATA INTEGRITY ARCHITECTURE The Pentium II processor system bus’ major address and data paths are protected by ten check bits, providing parity or ECC. Eight ECC bits protect the data bus. Single-bit data ECC errors are automatically corrected. A two-bit parity code protects the address bus. Any address parity error on the address bus when the request is issued can be optionally retried to attempt a correction.

  • Page 49: Bus Signals Protected Indirectly

    Some processors or other bus agents may enhance error detection or correction for the bus by checking for protocol violations. Pentium II processor system bus protocol errors are treated as fatal errors unless specifically stated otherwise.

  • Page 50: Hard-Error Response

    PENTIUM II SYSTEM BUS ECC ALGORITHM The Pentium II processor system bus uses an ECC code that can correct single-bit errors, detect double-bit errors, and detect all errors confined to one nibble (SEC-DED-S4ED). System designers may choose to detect all these errors, or a subset of these errors. They may also choose to use the same ECC code in L3 caches, main memory arrays, or I/O subsystem buffers.
  • Page 51 Configuration...

  • Page 53: Description

    This chapter describes configuration options for P6 family processor agents. A system may contain one or two Pentium II processors. Processors can also be used in FRC configurations, with two physical processors in a logical FRC unit. Both processors are connected to one Pentium II processor system bus.

  • Page 54: Output Tristate

    CONFIGURATION taking into account synchronization between multiple Pentium II processor system bus agents. Pentium II processor system bus agents have the following configuration options: • Output tristate {Hardware} • Execution of the processor’s built-in self test (BIST) {Hardware} • Data bus error-checking policy: enabled or disabled {Software} •...

  • Page 55: Data Bus Error Checking Policy

    5.1.7. BERR# Driving Policy for Initiator Bus Errors A Pentium II processor system bus agent can be enabled to drive the BERR# signal if it detects a bus error. After active RESET#, BERR# signal driving is disabled for detected errors. It may be enabled under software control.

  • Page 56: Bus Error Driving Policy For Initiator Internal Errors

    0FFFFFFF0H (4 GB–16). 5.1.14. FRC Mode Enable Pentium II processor system bus agents can be configured to support a mode in which FRC is disabled or a mode in which FRC is enabled. The processor enters FRC enabled mode if A5# is sampled active on the active-to-inactive transition of RESET#, otherwise it enters FRC disabled mode.

  • Page 57: Apic Mode

    ID supplied at configuration. The agent ID can be 0 or 1 for each processor in systems which support two processors. Each logical processor (not an FRC master/checker pair) on a particular Pentium II processor system bus must have a distinct agent ID. For processors supporting only two symmetric agents, the BREQ[1:0]# bus signals are connected to the two symmetric agents as shown in Table 5-2.

  • Page 58: Low Power Standby Enable

    CONFIGURATION At the RESET# signal’s active-to-inactive transition, system interface logic is responsible for assertion of the BREQ0# bus signal. BREQ1# bus signals remain deasserted. All processors sample their BR1# pin on the RESET signal’s active-to-inactive transition and determine their agent ID from the sampled value. If FRC is not enabled, then each physical processor is a logical processor.

  • Page 59: Software-Programmable Options

    CONFIGURATION and IGNNE# on the inactive-to-active transition of RESET# to determine the core-frequency to bus-frequency relationship and immediately begins the internal PLL lock mode. On the active-to-inactive transition of RESET#, the processor internally latches the inputs to allow the pins to be used for normal functionality. Effectively, these pins must meet a large setup time (1 ms) to the active-to-inactive transition of RESET#.
  • Page 60 CONFIGURATION Table 5-4. Pentium ® II Processor Family Power-On Configuration Register (Continued) Processor Processor Register Feature Active Signals Bits Read/Write Default Clock frequency ratios LINT0, A20M#, D25=0, D24, Read IGNNE# D23, D22 see Table 5-7 Low power standby enable Read/Write Enabled Table 5-5.

  • Page 61: Initialization Process

    CONFIGURATION 5.4. INITIALIZATION PROCESS After establishing configuration options, a processor executes the following initialization actions: • Synchronize the internal phase-locked loop (PLL) used to derive the processor clock from the bus clock. • Configure the parallel bus arbiter based on the processor’s agent ID and FRC enable pin. Configure the APIC bus arbiter ID with additional information available via APIC cluster ID.

  • Page 63: Test Access Port (Tap)

    Test Access Port (TAP)

  • Page 65: Interface

    CHAPTER 6 TEST ACCESS PORT (TAP) This chapter describes the implementation of the P6 family test access port (TAP) logic. The TAP complies with the IEEE 1149.1 (“JTAG”) test architecture standard. Basic functionality of the 1149.1-compatible test logic is described here, but this chapter does not describe the IEEE 1149.1 standard in detail.

  • Page 66: Accessing The Tap Logic

    TEST ACCESS PORT (TAP) Processor Boundary Scan Register Test Access BIST Result Port Device Identification Bypass Register Control Signals Instruction Decode Control Logic Instruction Register Controller Machine 000940 Figure 6-1. Simplified Block Diagram of Processor TAP Logic 6.2. ACCESSING THE TAP LOGIC The TAP is accessed through a 1149.1-compliant TAP controller finite state machine.

  • Page 67: Tap Controller Finite State Machine

    TEST ACCESS PORT (TAP) Run– Test– Test/Idle Logic Reset TMS 1 TMS 0 Select– Select– DR–Scan IR–Scan Capture–DR Shift–DR Capture–DR Shift–DR Exit1–DR Pause–DR Exit2–DR Exit1–DR Pause–DR Exit2–DR Update–DR Update–DR 000941 Figure 6-2. TAP Controller Finite State Machine Following is a brief description of each of the states of the TAP controller state machine. Refer to the IEEE 1149.1 standard for detailed descriptions of the states and their operation.

  • Page 68: Accessing The Instruction Register

    TEST ACCESS PORT (TAP) • Pause-IR: Allows shifting of the instruction register to be temporarily halted. The current instruction does not change. • Exit2-IR: This is a temporary state. The current instruction does not change. • Update-IR: The instruction which has been shifted into the Instruction Register is latched onto the parallel output of the Instruction Register on the falling edge of TCK.

  • Page 69: Processor Tap Instruction Register

    TEST ACCESS PORT (TAP) (MSB) Parallel Output (LSB) Actual Instruction Register Shift Register Fixed Capture Value 000942 Figure 6-3. Processor TAP Instruction Register Figure 6-4 shows the operation of the TAP instruction register during the Capture-IR, Shift- IR and Update-IR states of the TAP controller. Flip-flops within the instruction register which are updated in each mode of operation are shaded.

  • Page 70: Accessing The Data Registers

    TEST ACCESS PORT (TAP) shift register with “000001”) and Shift-IR operate on rising edges of TCK, and Update-IR (which updates the actual instruction register) takes place on the falling edge of TCK. Controller State Instruction IDCODE BYPASS 000944 Figure 6-5. TAP Instruction Register Access 6.2.2.

  • Page 71: Instruction Set

    TEST ACCESS PORT (TAP) 6.3. INSTRUCTION SET Table 6-1 contains descriptions of the encoding and operation of the TAP instructions. There are seven 1149.1-defined instructions implemented in the TAP. These instructions select from among four different TAP data registers — the boundary scan, BIST result, device ID, and bypass registers.

  • Page 72: Data Register Summary

    Device ID Register The Device ID register contains the processor device identification code in the format shown in Table 6-3. The manufacturer’s identification code is unique to Intel. The part number code is divided into four fields: V (2.8V supply), product type (an Intel Architecture compatible processor), generation (sixth generation), and model.

  • Page 73: Bist Result Boundary Scan Register

    ® For more information on Boundary Scan, refer to the Pentium II Processor Boundary Scan Description Language files at the Intel developer’s website at developer.intel.com. 6.5. RESET BEHAVIOR The TAP and its related hardware are reset by transitioning the TAP controller finite state machine into the Test-Logic-Reset state.
  • Page 74 TEST ACCESS PORT (TAP) The TAP can be transitioned to the Test-Logic-Reset state in any one of three ways: • Power on the processor. This automatically (asynchronously) resets the TAP controller. • Assert the TRST# pin at any time. This asynchronously resets the TAP controller. •...

  • Page 75: Electrical Specifications

    Electrical Specifications...

  • Page 77: Gtl+ Bus Topology

    0 or a logical 1, and is generated on the S.E.C. cartridge for the processor core. The processor contains termination resistors that provide termination for one end of the Pentium II processor system bus. See Table 8-1 for the bus termination voltage specifications for GTL+. Local V copies should be generated on the motherboard for all other devices on the GTL+ system bus.

  • Page 78: Clock Control And Low Power States

    7.2. CLOCK CONTROL AND LOW POWER STATES The Pentium II processor allows the use of AutoHALT, Stop-Grant, Sleep and Deep Sleep states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 7-2 for a visual representation of the Pentium II processor low power states.
  • Page 79 The return from the SMI handler can be to either Normal Mode or the AutoHALT Power Down state. See the Intel Architecture Software Developer’s Manual, Volume III: System Programming Guide (Order Number 243192) for more information. FLUSH# will be serviced during AutoHALT state and the processor will return to the AutoHALT state.

  • Page 80: Halt/Grant Snoop State — State 4

    HALT/Grant Snoop state. The processor will stay in this state until the snoop on the Pentium II processor system bus has been serviced (whether by the processor or another agent on the Pentium II processor system bus). After the snoop is serviced, the processor will return to the Stop-Grant state or AutoHALT Power Down state, as appropriate.

  • Page 81: Normal State - State 1

    The operating voltage of the processor core and of the L2 cache die differ from each other. There are two groups of power inputs on the Pentium II processor package to support the voltage difference between the two components in the package. There are also five pins defined on the package for voltage identification (VID).

  • Page 82: Decoupling Guidelines

    (defined in Table 7-6) while maintaining the specified tolerances (also defined in Table 7-6). 7.4.2. System Bus GTL+ Decoupling The Pentium II processor contains high frequency decoupling capacitance on the processor substrate; bulk decoupling must be provided for by the system motherboard for proper GTL+ ®...

  • Page 83: System Bus Clock And Processor Clocking

    Using CRESET# (CMOS reset on the baseboard), the circuit in Figure 7-4 can be used to share these configuration signals. The component used as the multiplexer must not have outputs that drive higher than 2.5V in order to meet the Pentium II processor’s 2.5V tolerant...

  • Page 84: Example Schematic For Clock Ratio Pin Sharing

    As shown in Figure 7-4, the pull-up resistors between the multiplexer and the processor (1 KΩ) force a ratio of 1/2 into the processor in the event that the Pentium II processor powers up before the multiplexer and/or the core logic. This prevents the processor from ever seeing a ratio higher than the final ratio.

  • Page 85: Mixing Processors Of Different Frequencies

    To ensure the system is ready for Pentium II processor variations, the range of values which are in BOLD in Table 7-2 must be supported. A smaller range will risk the ability of the system to migrate to a higher performance processor.
  • Page 86 ELECTRICAL SPECIFICATIONS Table 7-2. Voltage Identification Definition (1, 2, 3) Processor Pins VID4 VID3 VID2 VID1 VID0 CORE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1.80 1.85 1.90 1.95 2.00 2.05 No Core NOTES: 0 = Processor pin connected to V 1 = Open on processor;...
  • Page 87 VID signals to the converter input. See the Pentium II Processor Power Distribution Guidelines (Order Number 243332) for further information on power supply specifications for the Pentium II processor and future Slot 1 processors. ® 7.7.

  • Page 88: Asynchronous Vs. Synchronous For System Bus Signals

    PENTIUM II PROCESSOR SYSTEM BUS SIGNAL GROUPS In order to simplify the following discussion, the Pentium II processor system bus signals have been combined into groups by buffer type. All Pentium II processor system bus outputs are open drain and require a high-level source provided externally by the termination or pull-up resistor.
  • Page 89 TESTHI should be connected to 2.5V with 1K–10K ohm resistors. is not connected to the Pentium II processor. This supply is used for debug purposes only. SLOTOCC# is described in A.1.41. BSEL# should be connected at V See Appendix A for EMI pin descriptions.

  • Page 90: Test Access Port (Tap) Connection

    Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended that the Pentium II processor be first in the TAP chain and followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting a 2.5V input.
  • Page 91 The electrical and mechanical integrity of the substrate edge fingers is specified to last for 50 insertion/ extraction cycles. Intel has performed internal testing showing functionality of single S.E.C. cartridge processors after 5000 insertions. While insertion/extraction cycling above 50 insertions may cause an increase in the contact resistance (above 0.1 ohms) and a degradation in the material integrity of the edge finger gold plating, it is...
  • Page 92 ELECTRICAL SPECIFICATIONS Table 7-6. Pentium ® II Processor/Slot 1 Connector Voltage/Current Specifications Core Symbol Parameter Freq Unit Notes for processor core 2.80 2, 3, 15 CORE for L2 cache 3.135 3.30 3.465 Bus termination voltage 1.365 1.635 1.5V ±3%, ±9% Baseboard Baseboard voltage, static –0.070...
  • Page 93 /dt is measured at the Slot 1 connector pins. 14. Vcc and Icc are not used by the Pentium II processor. This supply is used for debug purposes only. 15. Use Typical Voltage Specification with tolerance level specification to provide correct voltage regulation to the processor.

  • Page 94: Gtl+ Signal Groups Dc Specifications

    ELECTRICAL SPECIFICATIONS Table 7-7. GTL+ Signal Groups DC Specifications Symbol Parameter Unit Notes Input Low Voltage –0.3 0.82 Input High Voltage 1.22 Output Low Voltage 0.60 Output High Voltage See V max in Table 8-1 Output Low Current 1, 2 Leakage Current ±100 µA...
  • Page 95 Timings at the processor edge fingers are specified by design characterization. See Appendix A for the Pentium II processor edge finger signal definitions. Table 7-9 through Table 7-14 list the AC specifications associated with the Pentium II processor system bus. The system bus AC specifications are broken into the following categories: Table 7-9 and Table 7-10 contain the system bus clock core frequency and cache bus frequencies;...
  • Page 96 ELECTRICAL SPECIFICATIONS Table 7-9. System Bus AC Specifications (Clock) (1, 2) Parameter Unit Figure Notes System Bus Frequency 66.67 All processor core frequencies BCLK Period 15.0 3, 4 T1B: BCLK to Core Logic Offset 0.78 Absolute Value (5, 6) BCLK Period Stability ±300 7, 8 BCLK High Time...
  • Page 97 133.33 66.67 300.00 150.00 NOTES: Contact your local Intel representative for the latest information on processor frequencies and/or frequency multipliers. While other bus ratios are defined, operation at frequencies other than those listed are not supported. Table 7-11. Pentium ®...

  • Page 98: System Bus Ac Specifications (Reset Conditions)

    ELECTRICAL SPECIFICATIONS Table 7-12. Pentium ® II Processor System Bus AC Specifications (CMOS Signal Group) (1, 2, 3) Parameter Unit Figure Notes T11: 2.5 Output Valid Delay 1.00 10.5 T12: 2.5 Input Setup Time 5.50 5, 6 T13: 2.5 Input Hold Time 1.75 T14: 2.5 Input Pulse Width, except...
  • Page 99 ELECTRICAL SPECIFICATIONS Table 7-14. System Bus AC Specifications (APIC Clock and APIC I/O) (1, 2) Parameter Unit Figure Notes T21: PICCLK Frequency 33.3 T21B: FRC Mode BCLK to PICCLK Offset T22: PICCLK Period 30.0 500.0 T23: PICCLK High Time 12.0 T24: PICCLK Low Time 12.0...
  • Page 100 ELECTRICAL SPECIFICATIONS Table 7-15. System Bus AC Specifications (TAP Connection) Parameter Unit Figure Notes T30: TCK Frequency 16.667 T31: TCK Period 60.0 T32: TCK High Time 25.0 @1.7V T33: TCK Low Time 25.0 @0.7V T34: TCK Rise Time (0.7V–1.7V) (2, 3) T35: TCK Fall Time (1.7V–0.7V)

  • Page 101: Bclk To Core Logic Offset

    ELECTRICAL SPECIFICATIONS NOTES FOR Figure 7-6 THROUGH Figure 7-13 1. Figure 7-6 through Figure 7-13 to be used in conjunction with Table 7-9 through Table 7-15. 2. All AC timings for the GTL+ signals are referenced to the BCLK rising edge at 0.70V at the processor edge fingers.

  • Page 102: System Bus Valid Delay Timings

    ELECTRICAL SPECIFICATIONS Signal Valid Valid T7, T11, T29 (Valid Delay) T14, T15 (Pulse Width) 1.0V for GTL+ signal group; 1.25V for CMOS, APIC and TAP signal groups 000762b Figure 7-7. System Bus Valid Delay Timings V Valid Signal T8, T12, T27 (Setup Time) T9, T13, T28 (Hold Time) 1.0V for GTL+ signal group;...

  • Page 103: Frc Mode Bclk To Picclk Timing

    ELECTRICAL SPECIFICATIONS 0.7 V BCLK 0.7 V PICCLK Lag = T21B (FRC Mode BCLK to PICCLK offset) 000919 Figure 7-9. FRC Mode BCLK to PICCLK Timing BCLK RESET# Configuration (A20M#, IGNNE#, Safe Valid LINT[1:0]) Configuration (A[14:5]#, BR0#, Valid FLUSH#, INIT#) T9 (GTL+ Input Hold Time) T8 (GTL+ Input Setup Time) T10 (RESET# Pulse Width)

  • Page 104: Power-On Reset And Configuration Timings

    ELECTRICAL SPECIFICATIONS BCLK CORE PWRGOOD RESET# Configuration Valid Ratio (A20M#, IGNNE#, LINT[1:0]) T15 (PWRGOOD Inactive Pulse Width) T10 (RESET# Pulse Width) T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time) 000765b Figure 7-11. Power-On Reset and Configuration Timings 7-28...

  • Page 105: Test Timings (Tap Connection)

    ELECTRICAL SPECIFICATIONS 1.8 V 1.25 V TDI, TMS Input Signals Output Signals T43 (All Non-Test Inputs Setup Time) T44 (All Non-Test Inputs Hold Time) T40 (TDO Float Delay) T37 (TDI, TMS Setup Time) T38 (TDI, TMS Hold Time) T39 (TDO Valid Delay) T41 (All Non-Test Outputs Valid Delay) T42 (All Non-Test Outputs Float Delay) 000766b...

  • Page 107: Gtl+ Interface Specifications

    GTL+ Interface Specifications...

  • Page 109: System Specification

    This section defines the new open-drain bus called GTL+. The primary target audience is designers developing systems using GTL+ devices such as the Pentium II processor and the 82440FX PCIset. This specification will also be useful for I/O buffer designers developing an I/O cell and package to be used on a GTL+ bus.

  • Page 110: System Bus Specifications

    Driver Receiver Driver Receiver Driver Receiver REF´ REF´ REF´ ® Pentium II Processor Core Logic Pentium II Processor External Resistor/ Divider Network NOTE: V is generated on the processor. 000945 Figure 8-1. Example Terminated Bus with GTL+ Transceivers 8.1.1. System Bus Specifications It is recommended to have the GTL+ bus routed in a daisy-chain fashion with termination resistors at each end of every signal trace.

  • Page 111: System Ac Parameters: Signal Quality

    The Pentium ® II processor contains GTL+ termination resistors at the end of the signal trace on the processor substrate. The Pentium II processor generates V , on the processor, by using a voltage divider on V supplied through the Slot 1 connector.

  • Page 112: Specifications For Signal Quality

    GTL+ INTERFACE SPECIFICATIONS Table 8-2. Specifications for Signal Quality Symbol Parameter Specification ® Maximum Signal Maximum Absolute voltage for the Pentium 2.5V Overshoot processor edge finger Maximum Signal Maximum Absolute voltage a signal extends below -0.7V Undershoot V SS (simulated without protection diodes). Settling Limit The maximum amount of ringing, at the receiving ±10% of (V OH -V OL )

  • Page 113: Ringback Tolerance

    GTL+ INTERFACE SPECIFICATIONS 8.1.2.1. RINGBACK TOLERANCE The nominal maximum ringback tolerated by GTL+ receivers is stated in Table 8-2, namely: no closer to V than a ±250 mV overdrive zone. This requirement is usually necessary to guarantee that a receiver meets its specified minimum setup time (T ), since setup time usually degrades as the magnitude of overdrive beyond the switching threshold (V ) is...
  • Page 114 GTL+ INTERFACE SPECIFICATIONS These parameters are defined as follows: τ is the minimum time that the input must spend, after crossing V at the High level, before by at least α, while ρ, δ, and φ (defined it can ring back, having overshot V IN_HIGH_MIN below) are at some preset values, all without increasing T by more than 0.05 ns.

  • Page 115: Ac Parameters: Flight Time

    GTL+ INTERFACE SPECIFICATIONS If, for any reason, the receiver cannot tolerate any ringback across the reference threshold ), then r would be a negative number, and δ may be infinite. Otherwise, expect an inverse (or near-inverse) relationship between ρ and δ, where the more the ringback, the shorter is the time that the ringback is allowed to last without causing the receiver to detect φ...

  • Page 116: Measuring Nominal Flight Time

    GTL+ INTERFACE SPECIFICATIONS An example of the simplest Flight Time measurement is shown in Figure 8-5. The receiver specification assumes that the signal maintains an edge rate greater than or equal to 0.3V/ns at the receiver chip pad in the overdrive region from V to V +200 mV for a rising edge and that there are no signal quality violations after the input crosses V...

  • Page 117: Flight Time Of A Rising Edge Slower Than 0.3V/Ns

    GTL+ INTERFACE SPECIFICATIONS The 0.3V/ns edge rate will be addressed later in this chapter, since it is related to the conditions used to specify a GTL+ receiver’s minimum setup time. What is meant by edge rate is neither instantaneous, nor strictly average. Rather, it can best be described for a rising edge—by imagining an 0.3V/ns line crossing V at the same moment that the signal crosses it, and extending to V...

  • Page 118: Extrapolated Flight Time Of A Non-Monotonic Rising Edge

    GTL+ INTERFACE SPECIFICATIONS If the signal is not monotonic while traversing the overdrive region (V to V +200 mV rising, or V to V –200 mV falling), or rings back into the overdrive region after crossing V , then flight time is determined by extrapolating back from the last crossing of ±...

  • Page 119: Extrapolated Flight Time Of A Non-Monotonic Falling Edge

    GTL+ INTERFACE SPECIFICATIONS Figure 8-8 shows a falling edge that rings back into the overdrive region after crossing V and the 0.8V/ns line used to extrapolate flight time. Since strict adherence to the edge rate specification is not required for Hi-to-Lo transitions, and some drivers’ falling edges are substantially faster than 0.8V/ns—at both the fast and slow corners—care should be taken when using the 0.8V/ns extrapolation.
  • Page 120 GTL+ INTERFACE SPECIFICATIONS The maximum acceptable Flight Time is determined on a net-by-net basis, and is usually different for each unique driver-receiver pair. The maximum acceptable Flight Time can be calculated using the following equation (known as the setup time equation): = Clock Period - T FLIGHT_MAX CO-MAX...

  • Page 121: General Gtl+ I/O Buffer Specification

    GTL+ INTERFACE SPECIFICATIONS 8.2. GENERAL GTL+ I/O BUFFER SPECIFICATION This specification identifies the key parameters for the driver, receiver, and package that must be met to operate in the system environment described in the previous section. All specifications must be met over all possible operating conditions including temperature, voltage, and semiconductor process.

  • Page 122: I/O Buffer Ac Specifications

    GTL+ INTERFACE SPECIFICATIONS 8.2.2. I/O Buffer AC Specifications Table 8-4 contains the I/O Buffer AC parameters. Table 8-4. I/O Buffer AC Parameters Symbol Parameter Units Figure Notes dV/dt Output Signal Edge Rate, rise V/ns 1, 2, 3 EDGE dV/dt Output Signal Edge Rate, fall V/ns 1, 2, 3 EDGE...

  • Page 123: Test Load For Measuring Output Ac Timings

    GTL+ INTERFACE SPECIFICATIONS Device Pin 1.5V 50 Ohms 50 Ohm Line Test Probe Device Package Interconnect Clock Device Under Test NOTE: This is specific to the Pentium ® processor. Other GTL+ components may be specified to a different test load. 000955 Figure 8-9.

  • Page 124: Minimum Setup And Hold Times

    GTL+ INTERFACE SPECIFICATIONS 8.2.3.2. MINIMUM SETUP AND HOLD TIMES Setup time for GTL+ (TSU) is defined as: The minimum time from the input signal pin crossing of V to the clock pin of the receiver crossing the 0.7V level, which guarantees that the input buffer has captured new data at the input pin, given an infinite hold time.

  • Page 125: Standard Input Lo-To-Hi Waveform For Characterizing Receiver Setup Time

    GTL+ INTERFACE SPECIFICATIONS Hold time for GTL+, T , is defined as: HOLD The minimum time from the clock pin of the receivers crossing of the 1.5V level to the receiver input signal pin crossing of V , which guarantees that the input buffer has captured new data at the receiver input signal pin, given an infinite setup time.

  • Page 126: Standard Input Hi-To-Lo Waveform For Characterizing Receiver Setup Time

    GTL+ INTERFACE SPECIFICATIONS start 1.5V Clk Ref +0.2 –0.2 Clock Time 000958 Figure 8-12. Standard Input Hi-to-Lo Waveform for Characterizing Receiver Setup Time The recommended procedure for extracting T is outlined below. If one employs HOLD additional steps, it would be beneficial that any such extra steps be documented with the results of this receiver characterization: The full receiver circuit must be used, comprising the input differential amplifier, any shaping logic gates, and the edge-triggered (or pulse-triggered) flip-flop.

  • Page 127: Receiver Ringback Tolerance

    GTL+ INTERFACE SPECIFICATIONS 8.2.3.3. RECEIVER RINGBACK TOLERANCE Refer to 8.1.2.1. for a complete description of the definitions and methodology for determining receiver ringback tolerance. 8.2.4. System-Based Calculation of Required Input and Output Timings Below are two sample calculations. The first determines T and T , while the CO-MAX...

  • Page 128: Calculating Target Thold

    They are package trace length, (the electrical distance from the pin to the die), and package capacitance. The specifications for package trace length and package capacitance are specified in the Pentium II I/O buffer models available from Intel’s website at www.intel.com. Please see your Intel representative for more information.

  • Page 129: Signal Quality Specifications

    Signal Quality Specifications...

  • Page 131: System Bus Clock (Bclk) Signal Quality Specifications

    CHAPTER 9 SIGNAL QUALITY SPECIFICATIONS Signals driven on the Pentium II processor system bus should meet signal quality specifications to ensure that the components read data properly and that incoming signals do not affect the long term reliability of the component. All wave terms described below are simulated at the contact to the processor edge fingers.

  • Page 132: Bclk, Tck Picclk Generic Clock Waveform At The Processor Edge Fingers

    SIGNAL QUALITY SPECIFICATIONS 000808 Figure 9-1. BCLK, TCK PICCLK Generic Clock Waveform at the Processor Edge Fingers...

  • Page 133: Gtl+ Signal Quality Specifications

    SIGNAL QUALITY SPECIFICATIONS 9.2. GTL+ SIGNAL QUALITY SPECIFICATIONS Table 9-2 and Figures 8-3 and 8-4 describe the GTL+ signal quality specifications for the Pentium II processor. Table 9-2. GTL+ Signal Groups Ringback Tolerance Parameter Unit Figure Notes α: Overshoot 8-3, 8-4 1, 2 τ:...

  • Page 134: Ringback Specification

    SIGNAL QUALITY SPECIFICATIONS Settling Limit Overshoot Rising-Edge Ringback Falling-Edge Ringback Settling Limit Time Undershoot 000767b Figure 9-2. Non-GTL+ Overshoot/Undershoot and Ringback Tolerance 9.3.2. Ringback Specification Ringback refers to the amount of reflection seen after a signal has switched. The ringback specification is the voltage that the signal rings back to after achieving its maximum absolute value.

  • Page 135: Settling Limit Guideline

    SIGNAL QUALITY SPECIFICATIONS Table 9-3. Signal Ringback Specifications for Non-GTL+ Signals Maximum Ringback Input Signal Group Transition (with Input Diodes Present) Figure 0 → 1 Non-GTL+ Signals 2.0 V 1 → 0 Non-GTL+ Signals 0.7 V 9.3.3. Settling Limit Guideline Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach before its next transition.

  • Page 137: Thermal Specifications And Design Considerations

    Thermal Specifications and Design Considerations...

  • Page 139: Thermal Specifications

    THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS The Pentium II processor has a thermal plate for heatsink attachment. The thermal plate interface is intended to provide for multiple types of thermal solutions. This chapter will provide the necessary data for a thermal solution to be developed. See Figure 10-1 for thermal plate location.

  • Page 140: Thermal Solution Performance

    Table 10-1. T is a function PLATE of the system design. Table 10-2 provides the resultant thermal solution performance for a 266 MHz Pentium II processor at different ambient air temperatures around the processor. 10-2...

  • Page 141: Measurements For Thermal Specifications

    To minimize these errors, the following approach is recommended: • Use 36 gauge or finer diameter K, T, or J type thermocouples. Intel’s laboratory testing was done using a thermocouple made by Omega* (part number: 5TC-TTK-36-36). •...

  • Page 142: Processor Thermal Plate Temperature Measurement Location

    THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS cover the location specified for T measurement, the thermocouple should be PLATE attached at a 0° angle (refer to Figure 10-3). Cover 2.673 Measure T PLATE Measure from edge of thermal plate. at this point. Approx.

  • Page 143: Cover Temperature Measurement

    Table 10-1. This temperature specification is meant to ensure correct and reliable operation of the processor. Figure 10-5 illustrates the hottest points on the S.E.C. cartridge cover. T thermal measurements for the Pentium II processor should be made COVER at these points.

  • Page 144: Thermal Solution Attach Methods

    THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS 1.31 Edge near Slot 1 connector 000966 Figure 10-5. Guideline Locations for Cover Temperature (T COVER Thermocouple Placement 10.3. THERMAL SOLUTION ATTACH METHODS The design of the thermal plate is intended to support two different attach methods — heatsink clips and Rivscrews*.

  • Page 145: Heatsink Clip Attach

    THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS Figure 10-6. Heatsink Attachment Mechanism Design Space 10.3.1. Heatsink Clip Attach Figure 10-7 and Figure 10-8 illustrate example clip designs to support a low profile and a full height heatsink, respectively. The clips attach the heatsink by engaging with the underside of the thermal plate.

  • Page 146: Processor With An Example Low Profile Heatsink Attached Using Spring Clips

    THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS Thermal Plate 0.089 Max Depth Spring Clip Processor Core Processor Substrate Cover All dimensions in inches. 000877a Figure 10-7. Processor with an Example Low Profile Heatsink Attached using Spring Clips 0.089 Max Depth Thermal Plate Spring Clip Processor Core Processor Substrate...

  • Page 147: Rivscrew* Attach

    THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS 10.3.2. Rivscrew* Attach The Rivscrew attach mechanism uses a specialized rivet that is inserted through a hole in the heatsink into the thermal plate. Upon insertion, a threaded fastener is formed that can be removed if necessary. For Rivscrew attachment, the maximum depth between the thermal plate and the bottom of the rivscrew mandrel is 0.125".

  • Page 148: General Rivscrew* Heatsink Mechanical Recommendations

    THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS ñ H ole is 4 x 0 .1 50 0 . 00 5 0 . 30 5 Heatsink A ll di me nsio ns in inc h es . 000903a Figure 10-11. General Rivscrew* Heatsink Mechanical Recommendations 10-10...

  • Page 149: Cartridge Mechanical Specifications

    S.E.C. Cartridge Mechanical Specifications...

  • Page 151: Cartridge Materials Information

    Table 11-3 and Table 11-4 provide the processor edge finger and Slot 1 connector signal definitions for the Pentium II processor. The signal locations on the Slot 1 edge connector are to be used for signal routing, simulation and component placement on the motherboard.

  • Page 152: S.e.c. Cartridge Materials

    S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS Table 11-1. S.E.C. Cartridge Materials S.E.C. Cartridge Piece Piece Material Maximum Piece Weight (Grams) Thermal Plate Aluminum 6063-T6 67.0 Latch Arms GE Lexan 940, 30% glass filled Less than 2.0 per latch arm Cover GE Lexan 940 24.0 Skirt GE Lexan 940...

  • Page 153: S.e.c. Cartridge—Thermal Plate And Cover Side Views

    S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS Left Latch Arm Right Latch Arm Cover Left Latch Arm Thermal Plate Right Latch Arm Cover Skirt 000893a Figure 11-1. S.E.C. Cartridge—Thermal Plate and Cover Side Views 11-3...

  • Page 154: S.e.c. Cartridge Top And Side Views

    S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS 001055a Figure 11-2. S.E.C. Cartridge Top and Side Views 11-4...

  • Page 155: S.e.c. Cartridge Bottom Side View

    S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS 001054a Figure 11-3. S.E.C. Cartridge Bottom Side View 11-5...

  • Page 156: S.e.c. Cartridge Thermal Plate Side Dimensions

    S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS 3.805 ±0.020 2.473 ±0.016 2.070 ±0.020 2X 0.127 1.235 ±0.005 ±0.020 2X 0.340 ±0.005 These dimensions are from 1.845 ±0.005 1.830 ±0.005 2X 0.265 ±0.005 the bottom of the substrate edge fingers 001053 001053a Figure 11-4. S.E.C. Cartridge Thermal Plate Side Dimensions 1.25 0.001 / 1.000 x 1.000 2.50...

  • Page 157: S.e.c. Cartridge Thermal Plate Attachment Detail Dimensions

    S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS 000312JBM Figure 11-6. S.E.C. Cartridge Thermal Plate Attachment Detail Dimensions 11-7...

  • Page 158: S.e.c. Cartridge Latch Arm, Thermal Plate Lug And Cover Lug Dimensions

    S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS 2X 0.238 ±0.010 2X 0.103 ± 0.005 2X 0.174 ±0.005 2X 0.647 2X 0.488 ±0.015 ±0.010 Left 2X 0.136 2X 0.058 ±0.005 ±0.005 2X 0.253 ±0.010 001056a Figure 11-7. S.E.C. Cartridge Latch Arm, Thermal Plate Lug and Cover Lug Dimensions 11-8...

  • Page 159: S.e.c. Cartridge Latch Arm, Cover And Thermal Plate Detail Dimensions

    S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS R 0.015 0.075 0.022 0.236 0.060 0.060 0.122 0.113 0.060 0.084 Detail A Detail B (Bottom Side View) 0.120 Min. 0.277 0.082 0.058 0.316 0.116 0.216 0.291 0.055 0.276 45° Detail D Detail C Detail E 001057a NOTE: All dimensions without tolerance information are considered reference dimensions only.

  • Page 160: S.e.c. Cartridge Substrate Dimensions (Skirt Not Shown For Clarity)

    S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS Thermal Plate Cover Pin A1 Pin A121 70° See Detail A Substrate +0.007 0.062 in Figure 11-11 –0.005 2.835 1.850 2.992 ±0.008 2.008 ±0.008 5.000 001059b NOTE: All dimensions without tolerance information are considered reference dimensions only. Figure 11-9.

  • Page 161: S.e.c. Cartridge Substrate—Detail A

    S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS 0.098 0.098 Pin A73 Pin A74 (0.010) 0.008 0.356 Min. 0.236 0.138 Min. 0.146 Max. 0.039 0.045 0.074 ±0.002 0.037 121 X 0.016 ±0.002 .20 .008 .05 .002 Pad to Pad 121 X 0.043 ±0.002 .20 .008 .05 .002 Pad to Pad 001060b...

  • Page 162: S.e.c. Cartridge Mark Locations (Processor Markings)

    S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS 2-D Matrix Mark pentium iCOMP® 2.0 index=YYY ® S ZN N N /X YZ O R D ER C O D E with MMX™ technology X XX X XX X X-N N N N pentium ® Dynamic Mark Area with MMX™...

  • Page 163: Processor Edge Finger Signal Listing

    S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS 11.2. PROCESSOR EDGE FINGER SIGNAL LISTING Table 11-3 is the processor substrate edge finger listing in order by pin number. Table 11-3. Signal Listing in Order by Pin Number Pin Name Signal Buffer Type Pin Name Signal Buffer Type VCC_VTT GTL+ V...
  • Page 164 S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS Table 11-3. Signal Listing in Order by Pin Number (Cont’d) Pin Name Signal Buffer Type Pin Name Signal Buffer Type DEP#[2] GTL+ I/O DEP#[1] GTL+ I/O DEP#[4] GTL+ I/O DEP#[3] GTL+ I/O DEP#[7] GTL+ I/O DEP#[5] GTL+ I/O VCC_CORE Processor Core V...
  • Page 165 S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS Table 11-3. Signal Listing in Order by Pin Number (Cont’d) Pin Name Signal Buffer Type Pin Name Signal Buffer Type D#[31] GTL+ I/O VCC_CORE Processor Core V D#[29] GTL+ I/O D#[30] GTL+ I/O D#[26] GTL+ I/O D#[27] GTL+ I/O D#[25]...
  • Page 166 S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS Table 11-3. Signal Listing in Order by Pin Number (Cont’d) Pin Name Signal Buffer Type Pin Name Signal Buffer Type A#[34] GTL+ I/O A#[29] GTL+ I/O A#[30] GTL+ I/O EMI Management A#[26] GTL+ I/O A#[31] GTL+ I/O A#[24] GTL+ I/O A#[27]...
  • Page 167 S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS Table 11-3. Signal Listing in Order by Pin Number (Cont’d) Pin Name Signal Buffer Type Pin Name Signal Buffer Type A107 REQ#[2] GTL+ I/O B107 DRDY# GTL+ I/O A108 REQ#[3] GTL+ I/O B108 RS#[0] GTL+ Input A109 HITM# GTL+ I/O...

  • Page 168: Signal Listing In Order By Signal Name

    S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS Table 11-4 is the processor substrate edge connector listing in order by signal name. Table 11-4. Signal Listing in Order by Signal Name Pin Name Signal Buffer Type Pin Name Signal Buffer Type A#[3] GTL+ I/O A#[29] GTL+ I/O A100...
  • Page 169 S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS Table 11-4. Signal Listing in Order by Signal Name (Cont’d) Pin Name Signal Buffer Type Pin Name Signal Buffer Type D#[2] GTL+ I/O D#[29] GTL+ I/O D#[3] GTL+ I/O D#[30] GTL+ I/O D#[4] GTL+ I/O D#[31] GTL+ I/O D#[5] GTL+ I/O...
  • Page 170 S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS Table 11-4. Signal Listing in Order by Signal Name (Cont’d) Pin Name Signal Buffer Type Pin Name Signal Buffer Type D#[56] GTL+ I/O D#[57] GTL+ I/O D#[58] GTL+ I/O D#[59] GTL+ I/O D#[60] GTL+ I/O D#[61] GTL+ I/O D#[62] GTL+ I/O...
  • Page 171 S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS Table 11-4. Signal Listing in Order by Signal Name (Cont’d) Pin Name Signal Buffer Type Pin Name Signal Buffer Type A110 Reserved Reserved for Future Use A114 Reserved Reserved for Future Use A118 Reserved Reserved for Future Use B110 HIT# GTL+ I/O...
  • Page 172 S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS Table 11-4. Signal Listing in Order by Signal Name (Cont’d) Pin Name Signal Buffer Type Pin Name Signal Buffer Type VCC_CORE Processor Core V B105 VCC_CORE Processor Core V VCC_CORE Processor Core V B113 VCC_L2 Other V VCC_CORE Processor Core V B117...

  • Page 173: Boxed Processor Specifications

    Boxed Processor Specifications...

  • Page 175: Introduction

    BOXED PROCESSOR SPECIFICATIONS 12.1. INTRODUCTION The Pentium II processor is also offered as an Intel Boxed processor. Intel Boxed processors are intended for system integrators who build systems from motherboards and standard components. The Boxed Pentium II processor will be supplied with an attached fan/heatsink.

  • Page 176: Mechanical Specifications

    ® II Processor in Retention Mechanism 12.2. MECHANICAL SPECIFICATIONS This section documents the mechanical specifications of the Boxed Pentium II processor fan/heatsink. 12.2.1. Boxed Processor Fan/Heatsink Dimensions The Boxed processor ships with an attached fan/heatsink. Clearance is required around the fan/heatsink to ensure unimpeded airflow for proper cooling.

  • Page 177: Side View Space Requirements For The Boxed Processor (Fan/Heatsink Supports Not Shown)

    BOXED PROCESSOR SPECIFICATIONS 1.291 Max (A) Fan Heatsink S.E.C. Cartridge Cover Slot 1 Connector 0.485 (B) 000890a Figure 12-2. Side View Space Requirements for the Boxed Processor (Fan/heatsink supports not shown) Power Cable 4.90 Max (D) Connector 2.19 (C) 1.25 000891a Figure 12-3.

  • Page 178: Boxed Processor Fan/Heatsink Weight

    BOXED PROCESSOR SPECIFICATIONS Measure ambient temperature 0.3” above center of fan inlet 0.40 Min Air Space (E) (both ends) Air Space 0.20 Min Fan Heatsink Air space S.E.C. Cartridge Cover 000892 Figure 12-4. Top View Space Requirements for the Boxed Processor Table 12-1.

  • Page 179: Boxed Processor Fan/Heatsink Support Dimensions

    BOXED PROCESSOR SPECIFICATIONS Any motherboard components placed in the area beneath the fan/heatsink supports must recognize the clearance (H) give in Table 12-3 below. Component height restrictions for passive heatsink support designs, as described in AP-588, Mechanical and Assembly Technology for S.E.C. Cartridge Processors (Order Number 243333), still apply. Motherboards designed for use by system integrators should not have objects installed in the heatsink support holes.

  • Page 180: Heatsink Support Hole Locations And Sizes

    BOXED PROCESSOR SPECIFICATIONS Slot 1 Connector 0.156 Thru 1.769 0.187 Thru 2.932 1.950 Recommendations: 0.300 dia. trace keepout --all external layers 0.250 dia. trace keepout --all internal layers All dimensions in inches. 000875a Figure 12-5. Heatsink Support Hole Locations and Sizes 12-6...

  • Page 181: Side View Space Requirements For Boxed Processor Fan/Heatsink Supports

    BOXED PROCESSOR SPECIFICATIONS 2.261 (G) 0.275 DIA (J) (0.300 MAX) 0.060 (M) 0.430 (H) 0.060 (L) 0.240 (K) 1.769 000804a Figure 12-6. Side View Space Requirements for Boxed Processor Fan/Heatsink Supports 12-7...

  • Page 182: Boxed Processor Requirements

    BOXED PROCESSOR SPECIFICATIONS 4.084 (N) 0.600 (P) 0.400 (Q) 000805 Figure 12-7. Top View Space Requirements for Boxed Processor Fan/Heatsink Supports 12.3. BOXED PROCESSOR REQUIREMENTS 12.3.1. Fan/Heatsink Power Supply The Boxed processor’s fan/heatsink requires a +12V power supply. A fan power cable is shipped with the Boxed processor to draw power from a power header on the motherboard.

  • Page 183: Boxed Processor Fan/Heatsink Power Cable Connector Description

    BOXED PROCESSOR SPECIFICATIONS Signal Straight square pin, 3-pin terminal housing with polarizing ribs and friction locking ramp. +12V 0.100" pin pitch, 0.025" square pin width. SENSE Waldom*/Molex* P/N 22-01-3037 or equivalent. Match with straight pin, friction lock header on motherboard Waldom/Molex P/N 22-23-2031, AMP* P/N 640456-3, or equivalent.

  • Page 184: Thermal Specifications

    BOXED PROCESSOR SPECIFICATIONS Slot 1 Connector 1.439 Fan power connector location (1.56 inches above motherboard) 1.449 r = 4.75 inches Motherboard fan power header should be positioned within 4.75 inches of fan power connector (lateral distance) 000913a Figure 12-9. Recommended Motherboard Power Header Placement Relative to Fan Power Connector and Slot 1 12.4.

  • Page 185: Integration Tools

    Integration Tools...

  • Page 187: Primary Function

    13.1. IN-TARGET PROBE (ITP) FOR THE PENTIUM PROCESSOR An In-Target Probe (ITP) for the Pentium II processor is a debug tool which allows access to on-chip debug features via a small port on the system board called the debug port. The ITP communicates to the processor through the debug port using a combination of hardware and software.

  • Page 188: Debug Port Connector Description

    INTEGRATION TOOLS PCI Add-In Card 2m Cable Plugs in to your host PC (12.5 in.) 2 in. Cable Debug Port Connector Connects to Debug Port on target board Buffer Board 000816a Figure 13-1. Hardware Components of the ITP 13.1.2. Debug Port Connector Description The ITP connects to the system through the debug port.

  • Page 189: Debug Port Signal Notes

    The signal should be pulled up (Intel recommends a 240Ω resistor, but system designers will need to fine tune specific system designs) to meet two considerations: (1) the signal must be able to meet Vol of the system, and (2) it must allow the signal to meet the specified rise time.

  • Page 190: Debug Port Pinout Description And Requirements 1

    INTEGRATION TOOLS Table 13-1. Debug Port Pinout Description and Requirements Name Description Specification Requirement Notes • RESET# Reset signal from MP Terminate signal properly at Connected to high speed cluster to ITP. the debug port comparator (biased at 2/3 of the level found at the POWERON •...
  • Page 191 INTEGRATION TOOLS Table 13-1. Debug Port Pinout Description and Requirements (Cont’d) Name Description Specification Requirement Notes • Test data output signal from Add 150 ohm pull-up resistor Operates synchronously with ® last component in boundary (to Vcc TCK. Each Pentium scan chain of MP cluster to processor has a 25-ohm driver.
  • Page 192 INTEGRATION TOOLS Table 13-1. Debug Port Pinout Description and Requirements (Cont’d) Name Description Specification Requirement Notes • BCLK Bus clock from the MP Use a separate driver to drive Separate driver is used to avoid cluster; used to signal to the debug port loading issues associated with synchronize BCLK with the having the ITP either installed or...

  • Page 193: Signal Note 7: Tck

    INTEGRATION TOOLS CC_2.5 CC_2.5 Slot 1 Connector A 1 kΩ ITP Port 47Ω Motherboard Trace or TMS 47Ω Resistors Located < 1" from ITP Port Slot 1 Connector B Motherboard Trace Figure 13-4. TCK/TMS with Daisy Chain Configuration, 2-Way MP Configuration 13.1.4.3.

  • Page 194: Debug Port Layout

    INTEGRATION TOOLS Debug Port Pentium Pentium II ® Processor Processor (2.5 V) 000796a Figure 13-5. TCK with Daisy Chain Configuration 13.1.5. Debug Port Layout Figure 13-6 shows the simplest way to layout the debug port in a multiprocessor system. In this example, two processors are the only components in the system boundary scan chain.

  • Page 195: Generic Dp System Layout For Debug Port Connection

    INTEGRATION TOOLS PREQ1# PRDY1# TRST# PREQ3# BCLK RESET# PRDY3# PREQ2# PRDY2# RESET# BCLK TRST# PREQ1# **BSEN# PRDY1# DBRESET# PREQ0# **DBINST# PREQ0# PRDYY0# POWERON PRDY0# TRST# BCLK RESET# NOTE: See Table 13-1 for recommended resistor values. 000798c Figure 13-6. Generic DP System Layout for Debug Port Connection 13-9...

  • Page 196: Signal Quality Notes

    If the Pentium II processor boundary scan signals are used elsewhere in the system, then the TDI, TMS, TCK, and TRST# signals from the debug port should be isolated from the system signals with multiplexers as discussed earlier.

  • Page 197: Using Boundary Scan To Communicate To The Processor

    The LAI562 integration tool has been designed such that an extra load will be presented on the CMOS signals connected to the Slot 1 connector. If the LAI562 tool is not being used this issue can be ignored. However, be aware that if you send a system to Intel for debug, the 13-11...

  • Page 198: Lai Probe Input Circuit

    INTEGRATION TOOLS absence of the required workarounds will prohibit debug assistance from Intel. The following list of signals are affected: PREQ#, TCK, TDI, TDO, TMS, TRST#, INIT#, FLUSH#, STPCLK#, PICCLK, PICD[1:0]#, LINT[0]/INTR, LINT[1]/NMI, IERR#, SMI#, PWRGOOD, THERMTRIP#, SLP#, FERR#, IGNNE# and A20M#.

  • Page 199: Pentium ® Ii Processor Integration Tool Mechanical Keep Out Volume Thermal Plate Side View

    INTEGRATION TOOLS Cable continues up. 1.375 Integration Tool Volume 0.025 Slot 1 Edge Connector Thermal Plate Side View All dimensions in inches. 000839c Figure 13-11. Pentium ® II Processor Integration Tool Mechanical Keep Out Volume— Thermal Plate Side View 13-13...
  • Page 200 INTEGRATION TOOLS 1.375 2.25 1.375 Integration Tool Volume 0.025 Slot 1 Edge Cover Side View Connector All dimensions in inches. 000840b Figure 13-12. Pentium ® II Processor Integration Tool Mechanical Keep Out Volume— Cover Side View 13-14...

  • Page 201: Side View

    INTEGRATION TOOLS 2.00 0.15 0.35 Cable continues upward 1. 7 0.385 0.65 Side View All dimensions in inches. 000838b Figure 13-13. Pentium ® II Processor Integration Tool Mechanical Keep Out Volume— Side View 13-15...
  • Page 203 Advanced Features...
  • Page 205 For software developers designing other categories of software, this information does not apply. All of the required program development details are provided in the Intel Architecture Software Developer's Manual: Volume 2, Instruction Set Reference (Order Number 243191), which is publicly available from the Intel Corporation Literature Center.
  • Page 207 Signals Reference...
  • Page 209 APPENDIX A SIGNALS REFERENCE This appendix provides an alphabetical listing of all Pentium II processor signals. The tables at the end of this appendix summarize the signals by direction: output, input, and I/O. A.1. ALPHABETICAL SIGNALS LISTING A.1.1. A[35:0]# (I/O) The A[35:3]# (Address) signals define a 2 -byte physical memory address space.
  • Page 210 The AERR# (Address Parity Error) signal is observed and driven by all Pentium II processor system bus agents, and if used, must connect the appropriate pins on all Pentium II processor system bus agents. AERR# observation is optionally enabled during power-on configuration;...
  • Page 211 Since multiple agents might need to request a bus stall at the same time, BNR# is a wire-OR signal which must connect the appropriate pins of all Pentium II processor system bus agents. In order to avoid wire-OR glitches associated with simultaneous edge transitions driven by multiple drivers, BNR# is activated on specific clock edges and sampled on specific clock edges.

  • Page 212: A-1. Br0#(I/O), Br1#, Br2#, Br3# Signals Rotating Interconnect

    A.1.12. BPRI# (I) The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the Pentium II processor system bus. It must connect the appropriate pins of all Pentium II processor system bus agents.
  • Page 213 A.1.15.1. LINE TRANSFERS A line transfer reads or writes a cache line, the unit of caching on the Pentium II processor system bus. For current products, this is 32 bytes aligned on a 32-byte boundary. While a line is always aligned on a 32-byte boundary, a line transfer need not begin on that boundary. For a line transfer, A[35:3]# carry the upper 33 bits of a 36-bit physical address.
  • Page 214 The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving data on the Pentium II processor system bus to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on all Pentium II processor system bus agents.
  • Page 215 A.1.21. FERR# (O) The FERR# (Floating-point Error) signal is asserted when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using DOS-type floating-point error reporting.
  • Page 216 The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop operation results, and must connect the appropriate pins of all Pentium II processor system bus agents. Any such agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together.
  • Page 217 The LOCK# signal indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of all Pentium II processor system bus agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction end of the last transaction.
  • Page 218 SIGNALS REFERENCE to retain ownership of the Pentium II processor system bus throughout the bus locked operation and ensure the atomicity of lock. Bit 31 of the Model Specific Register (MSR) at address 33h to 1 will prevent LOCK# from being asserted when locked transactions, which are split across a cache line boundary, are issued from the processor.

  • Page 219: A-1. Pwrgood Relationship At Power-On

    SIGNALS REFERENCE A.1.37. PWRGOOD (I) The PWRGOOD (Power Good) signal is a 2.5V tolerant processor input. The processor requires this signal to be a clean indication that the clocks and power supplies (Vcc CORE etc.) are stable and within their specifications. Clean implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification.
  • Page 220 A.1.40. RP# (I/O) The RP# (Request Parity) signal is driven by the request initiator, and provides parity protection on ADS# and REQ[4:0]#. It must connect the appropriate pins of all Pentium II processor system bus agents. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low.

  • Page 221: A-4. Slot 1 Occupation Truth Table

    SIGNALS REFERENCE of VID[4:0]= 11111 (see Section 7.6.), a system can determine if a Pentium II connector is occupied, and whether a processor core is present. See Table A-4 for states and values for determining the type of package in the Slot 1 connector.
  • Page 222 SIGNALS REFERENCE A.1.47. TCK (I) The TCK (Test Clock) signal provides the clock input for the Pentium II processor Test Bus (also known as the Test Access Port). A.1.48. TDI (I) The TDI (Test Data In) signal transfers serial test data into the Pentium II processor. TDI provides the serial input needed for JTAG specification support.
  • Page 223 The VID pins are needed to cleanly support voltage specification variations on Pentium II processors. See Table 7-2 for definitions of these pins. The power supply must supply the voltage that is requested by these pins, or disable itself.
  • Page 224 SIGNALS REFERENCE A.2. SIGNAL SUMMARIES The following tables list attributes of the Pentium II processor output, input and I/O signals. Table A-5. Output Signals Name Active Level Clock Signal Group FERR# Asynch CMOS Output IERR# Asynch CMOS Output PRDY# BCLK...
  • Page 225 SIGNALS REFERENCE Table A-6. Input Signals Name Active Level Clock Signal Group Qualified A20M# Asynch CMOS Input Always BPRI# BCLK GTL+ Input Always BR1# BCLK GTL+ Input Always BCLK High — Clock Always DEFER# BCLK GTL+ Input Always FLUSH# Asynch CMOS Input Always IGNNE#...

  • Page 226: A-7. Input/Output Signals (Single Driver)

    SIGNALS REFERENCE Table A-7. Input/Output Signals (Single Driver) Name Active Level Clock Signal Group Qualified A[35:3]# BCLK GTL+ I/O ADS#, ADS#+1 ADS# BCLK GTL+ I/O Always AP[1:0]# BCLK GTL+ I/O ADS#, ADS#+1 BR0# BCLK GTL+ I/O Always BP[3:2]# BCLK GTL+ I/O Always BPM[1:0]# BCLK...

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