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®
®
Intel
Pentium
M Processor and Intel
Platform Power Delivery Guidelines
•
thirteen 0.1 µF capacitors are recommended (with 900 pH to 1.1 nH inductance) and should be
evenly spaced for the System Bus. At least seven of the capacitors must be within 0.5 inch of
the outer row of balls to the MCH.
11.4.3
DDR (2.5 V Power Plane)
Seven 0.1µF capacitors are recommended (with 900 pH to 1.1 nH inductance) to be placed under
the MCH for DDR 2.5 V power plane decoupling (see
distribute placement of decoupling capacitors among the DDR interface signal field. It is
recommended that the designer use ceramic capacitor 0402 or 0603 package type. In addition to the
minimum decoupling capacitors under the MCH, for dual channel, the designer should place a
maximum of twenty-one evenly spaced capacitors for both DDR channels, and at least ten must be
within 0.5 inch of the outer row of balls to the MCH. For single channel, the designer should place
a maximum of eleven evenly spaced capacitors for channel 'A', and at least five must be within 0.5
inch of the outer row of balls to the MCH.
Figure 137.
MCH Decoupling (Backside View)
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E7501 Chipset Platform
HI_A–D
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DDR A
Figure
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Design Guide
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