Intel Pentium M Processor Design Manual page 15

45 Single Channel Source Clocked Signal Group Routing Guidelines.......................................... 101
46 Single Channel Chip Select Routing Guidelines.......................................................................102
47 Single Channel Clock Enable Routing Guidelines.................................................................... 103
48 Single Channel Receive Enable Routing Guidelines ................................................................104
49 DDRCOMP Routing Guidelines................................................................................................ 105
50 DDRCVO Routing Guidelines................................................................................................... 107
51 Hub Interface 2.0 Signal/Strobe Association ............................................................................114
52 Hub Interface 2.0 Signal Groups .............................................................................................. 114
53 Hub Interface 2.0 Routing Parameters ..................................................................................... 114
54 Hub Interface 2.0 Reference Circuit Specifications .................................................................. 118
55 Hub Interface 2.0 RCOMP Resistor Values.............................................................................. 119
56 Hub Interface 1.5 Signal Groups .............................................................................................. 120
57 Hub Interface 1.5 Routing Parameters ..................................................................................... 121
58 Hub Interface 1.5 Reference Circuit Specifications .................................................................. 121
59 Hub Interface 1.5 RCOMP Resistor Values.............................................................................. 122
60 PCI/PCI-X Frequencies ............................................................................................................ 123
61 Simulated Timing Critical Signals ............................................................................................. 124
62 PCI/PCI-X Mode and Frequency Ordering ............................................................................... 124
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63 Intel P64H2 PCI/PCI-X Length Requirements........................................................................ 125
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64 Intel P64H2 Hot-Plug Length Requirements .......................................................................... 126
65 PCI-X Riser Card Length Requirements...................................................................................127
66 Device Down Before PCI-X Riser Card Length Requirements................................................. 127
67 Device Down After PCI-X Riser Card Length Requirements.................................................... 128
68 Device Down with Stub Before PCI-X Riser Card Length Requirements ................................. 128
69 Two Devices Down Length Requirements................................................................................ 129
70 Hot-Plug Clock Routing Length Parameters............................................................................. 129
71 No Hot-Plug Clock Routing Length Parameters .......................................................................130
72 Loop Clock Configuration Routing Length Parameters ............................................................ 131
73 SMBus Address Configuration.................................................................................................. 132
74 Hot-Plug Mode.......................................................................................................................... 136
75 Frequency Matrix for Non-Hot Plug Designs ............................................................................137
76 Single-Slot Parallel Mode Hot-Plug Signal Table .....................................................................138
77 Hot-Plug Controller Output Signal Reset Values ...................................................................... 139
78 Dual-Slot Parallel Mode Hot-Plug Signals Table ...................................................................... 143
79 Shift Register Input Data........................................................................................................... 147
80 Bus Capacitance Reference Chart ........................................................................................... 162
81 Bus Capacitance/Pull-Up Resistor Relationship .......................................................................162
82 Internal LAN Layout Guidelines ................................................................................................ 168
83 LAN Design Guide Section Reference ..................................................................................... 168
84 LCI Routing Parameter Summary............................................................................................. 170
85 Recommended ITP700FLEX Signal Terminations ................................................................... 183
86 Power Summary ....................................................................................................................... 191
87 VID vs. V
CC_CORE
88 V Decoupling Guidelines ............................................................................................ 202
CC_CORE
89 VCCP Decoupling Guidelines................................................................................................... 202
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90 Intel ICH3-S Power Rail Terminology..................................................................................... 210
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91 Intel ICH3-S Decoupling Recommendations .......................................................................... 210
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92 Intel P64H2 Max Sustained Currents ..................................................................................... 212
93 Decoupling Capacitor Recommendations ................................................................................ 212
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94 Intel Pentium
Design Guide
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Intel Pentium
Voltage ....................................................................................................... 193
M Processor Signal Package Lengths............................................................ 232
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M Processor and Intel
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E7501 Chipset Platform
Contents
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