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regulator may be programmed through an external resistor network. See
to set the highest output voltage in conjunction with the selection of R5 and R6 in the resistor
network. Ensure R5 and R6 are precision resistors with +/- 0.1% tolerance.
Figure 129.
V
Block Diagram
CCP
11.3.5
Thermal Power Dissipation
Power dissipation has traditionally been a thermal/mechanical challenge for embedded system
designers. The amount of current required from the processor power delivery circuit and the heat
generated by processors has increased as processor frequencies go up and the silicon process
geometry shrinks. The package of any integrated device may only dissipate so much heat into the
surrounding environment. The temperature of a device, such as a processor power delivery circuit-
switching transistor, is a balance of heat being generated by the device and its ability to shed heat
either through radiation into the surrounding air or by conduction into the circuit board. Increased
power may effectively raise the temperature of the processor power delivery circuits. Switching
transistor die temperatures may exceed the recommended operating value when the heat cannot be
removed from the package effectively.
As the current demands for higher frequency and performance processors increases, the amount of
power dissipated (i.e., heat generated) in the processor power delivery circuit is starting to become
of concern for Applied Computing system, thermal and electrical design engineers. The high input
voltage, low duty factor inherent in power supply designs leads to increasing power dissipation
losses in the output stage of the traditional buck regulator topology used in the industry today.
These losses may be attributed to three main areas of the processor power delivery circuit. The
switching MOSFET dissipates a significant amount of power during switching of the top control
MOSFET, power dissipation resulting from drain to source resistance (R
the bottom synchronous MOSFET, and the power dissipation generated through the magnetic core
and windings of the main power inductor.
There has been significant improvement in the switching MOSFET technology to lower gate
charge of the control MOSFET allowing them to switch faster thus reducing switching losses.
Improvements in lowering the R
reduced DC losses. The Direct Current Resistance (DCR) of the power inductor has been reduced,
as well, to lower the amount of power dissipation in the circuit's magnetic.
Design Guide
®
Intel
Pentium
®
Intel
IMVP-IV
Voltage
Regulator
R6*
V
REF
DS(ON)
®
M Processor and Intel
Platform Power Delivery Guidelines
V
CCP
* +/- 0.1%
Tolerance
Recommended
R5*
parametric of the synchronous MOSFET have resulted in
®
E7501 Chipset Platform
Figure
129. VREF is used
®
®
Intel
Pentium
M
Processor
MCH
®
Intel
ICH3
ITPFLEX700
) DC losses across
DS-ON
195
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