Intel Pentium M Processor Design Manual page 200

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Intel Pentium M Processor and Intel
Platform Power Delivery Guidelines
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Bulk capacitors for V
bypass capacitors may be clustered along the high current paths between the sense resistor and
the processor. Clusters may have copper fill areas between capacitors. This provides additional
opportunities for vias – don't stop at three.
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Some controllers sense the load on Vcc by monitoring the voltage drop across the sense
resistor with a Kelvin connection. The two feedback traces do not handle a high current, but
must be of equal lengths to get an accurate load measurement. Connect the feedback signal
traces as close as possible to both ends of the sense resistor. While the feedback traces do not
handle high current, they are high impedance and susceptible to interference from electrical
and magnet noise. Avoid routing these traces near the power inductor and avoid routing
through vias.
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The sense resistor is to be placed as close to the inductor as possible, followed by the first two
bulk capacitors.
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The lead frame in the power MOSFETs is used to dissipate heat. To do this each of the power
MOSFETs requires one square inch of copper.
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Avoid ground loops as they pick up noise. Use star or single point grounding. The source of
the lower (Synchronous bottom MOSFET) is an ideal point where the input and output ground
planes may be connected.
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Keep the inductor-switching node small by placing the output inductor, switching top
MOSFET and synchronous bottom MOSFETs close together on the same copper fill.
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The MOSFET enable/gate traces to the driver must be as short (less than one inch), straight,
and wide as possible (20 to 25 mils). Ideally, the driver has to be placed right next to the
MOSFETs. Circuits using multiple top or bottom MOSFETs need to have the gate traces
serpentined so the all the traces going to the top MOSFETs Gates and most especially the
bottom MOSFETs gates are the same length.
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Use the bulk capacitors for the voltage regulator and use multiple layer traces with heavy
copper to keep the parasitic resistance low. Use a minimum of three vias per connection on
each bulk capacitor.
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Place the top MOSFET drains as close to the VDC-input capacitors as possible.
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The sense resistor has to be wide enough to carry the full load current. A minimum of 1 via per
Amp to the Vcc plane should be used. Use more when space permits.
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Use solid 2-oz. copper fill under drain and source connections of the top and bottom
MOSFETs.
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The voltage regulator is usually left to the last moment. Often the allocated area is too small, a
narrow strip and the location poor. These factors combine so that the design flow, described
above usually cannot be followed.
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General Rule: Copper fill is good. Fill the PCB with metal. There should be no large areas of
the board without metal. Increase the width of the grounds, V
any blank spots. Large metal fill areas allow the voltage regulator to improve its heat radiation
thus run cooler. Large copper fill areas have other benefits too, including reducing series
resistance and inductance, capturing and dissipating RF energy by allowing eddy currents to
flow.
200
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E7501 Chipset Platform
need three vias per pad when vias are not shared. Clusters of bulk and
CC
and other power rails to fill
CC
Design Guide