Pcirst# Implementation; Intel ® P64H2 Power Sequencing Requirement - Intel Pentium M Processor Design Manual

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Figure 146. Intel P64H2 3.3 V PCI/PCI-X (VCC_3.3) Capacitor Placement on Backside
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NOTE: The outlined area in the figure is the 3.3 V plane. Place at least five 0.1 µF capacitors in this area.
11.6.3

PCIRST# Implementation

PCI-X requires a 100 ms delay from valid power (PWRGD) to reset deassertion (PCIRST#). The
system design must ensure this requirement is met.
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The Intel
strongly recommends customers measure this timing relationship on their boards. Failure to meet
this guideline may result in a system failing to boot.
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11.6.4 Intel
The 1.8 V voltage must be valid before the first CLK66 pulse is driven to the Intel P64H2. This
may be ensured by gating the CK408 clocks using a power good signal from the 1.8 V regulator. If
the first CLK66 pulse is driven before 1.8 V is valid, the Intel P64H2 PLL may fail to correctly
lock.
The 1.8 V must drop with or before 3.3 V. This may be achieved by deriving 1.8 V from 3.3 V.
When 1.8 V drops after 3.3 V, a noise spike on PCIRST# approaches V
Design Guide
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Intel Pentium
A1
P64H2 reset must be deasserted within 60 ns of the MCH reset deassertion. Intel
P64H2 Power Sequencing Requirement
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M Processor and Intel
Platform Power Delivery Guidelines
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E7501 Chipset Platform
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0.1uF
AD1
minimum levels.
IH
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